Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TSSOP 16

12-Bit, 8-Channel Sampling

ANALOG-TO-DIGITAL CONVERTER

with I

™

Interface

FEATURES

● 8-CHANNEL MULTIPLEXER

● 50kHz SAMPLING RATE

● NO MISSING CODES

● 2.7V TO 5V OPERATION

● INTERNAL 2.5V REFERENCE

● I

C INTERFACE SUPPORTS:

Standard, Fast, and High-Speed Modes

● TSSOP-16 PACKAGE

APPLICATIONS

● VOLTAGE-SUPPLY MONITORING

● ISOLATED DATA ACQUISITION

● TRANSDUCER INTERFACES

● BATTERY-OPERATED SYSTEMS

● REMOTE DATA ACQUISITION

DESCRIPTION

The ADS7828 is a single-supply, low-power, 12-bit data

acquisition device that features a serial I

C interface and an

8-channel multiplexer. The Analog-to-Digital (A/D) converter

features a sample-and-hold amplifier and internal,

asynchronous clock. The combination of an I

C serial,

2-wire interface and micropower consumption makes the

ADS7828 ideal for applications requiring the A/D converter to

be close to the input source in remote locations and for

applications requiring isolation. The ADS7828 is available in

a TSSOP-16 package.

ADS7828

SBAS181C – NOVEMBER 2001 - REVISED MARCH 2005

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SAR

2.5V V

REF

Serial

Interface

SDA

Comparator

S/H Amp

REF

/REF

OUT

SCL

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

CDAC

8-Channel

MUX

Buffer

S7828

C is a trademark of Koninklijke Philps Electronics N.V. All other trademarks are the property of their respective owners.

Summary of content (22 pages)

PAGE 1
ADS7828 ADS 78 ® 28 SBAS181C – NOVEMBER 2001 - REVISED MARCH 2005 12-Bit, 8-Channel Sampling ANALOG-TO-DIGITAL CONVERTER with I2C™ Interface DESCRIPTION FEATURES ● ● ● ● ● ● 8-CHANNEL MULTIPLEXER 50kHz SAMPLING RATE NO MISSING CODES 2.7V TO 5V OPERATION INTERNAL 2.5V REFERENCE I2C INTERFACE SUPPORTS: Standard, Fast, and High-Speed Modes ● TSSOP-16 PACKAGE The ADS7828 is a single-supply, low-power, 12-bit data acquisition device that features a serial I2C interface and an 8-channel multiplexer.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) +VDD to GND ........................................................................ –0.3V to +6V Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V Operating Temperature Range ...................................... –40°C to +105°C Storage Temperature Range ......................................... –65°C to +150°C Junction Temperature (TJ max) ....................................................
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ELECTRICAL CHARACTERISTICS: +2.7V At TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted. ADS7828E PARAMETER ANALOG INPUT Full-Scale Input Scan Absolute Input Range CONDITIONS MIN Positive Input - Negative Input Positive Input Negative Input 0 –0.2 –0.
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ELECTRICAL CHARACTERISTICS: +5V At TA = –40°C to +85°C, +VDD = +5.0V, VREF = External +5.0V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted. ADS7828E PARAMETER ANALOG INPUT Full-Scale Input Scan Absolute Input Range CONDITIONS MIN Positive Input - Negative Input Positive Input Negative Input 0 –0.2 –0.2 Capacitance Leakage Current ADS7828EB MAX MIN VREF +VDD + 0.2 +0.2 0 –0.2 –0.
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TIMING DIAGRAM SDA tBUF tLOW tF tR tHD; STA tSP SCL tHD; STA tSU; STA tHD; DAT STOP tHIGH tSU; STO tSU; DAT START REPEATED START TIMING CHARACTERISTICS(1) At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. PARAMETER SYMBOL CONDITIONS SCL Clock Frequency fSCL Standard Mode Fast Mode High-Speed Mode, CB = 100pF max High-Speed Mode, CB = 400pF max Bus Free Time Between a STOP and START Condition tBUF Standard Mode Fast Mode 4.7 1.
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TIMING CHARACTERISTICS(1) (Cont.) At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. PARAMETER Rise Time of SDA Signal Fall Time of SDA Signal Setup Time for STOP Condition SYMBOL CONDITIONS MIN MAX UNITS tRDA Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 20 + 0.1CB 10 20 1000 300 80 160 ns ns ns ns Standard Mode Fast Mode High-Speed Mode, CB = 100pF max(2) High-Speed Mode, CB = 400pF max(2) 20 + 0.
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TYPICAL CHARACTERISTICS TA = +25°C, VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT: fIN = 1kHz, 0dB) INTEGRAL LINEARITY ERROR vs CODE (2.5V Internal Reference) 0.00 2.00 1.50 Amplitude (dB) 1.00 ILE (LSB) –40.00 –80.00 0.50 0.00 –0.50 –1.00 –1.50 –120.0 –2.00 0 10 20 25 0 1024 2048 Output Code Frequency (kHz) 2.00 2.00 1.50 1.50 1.00 1.00 0.50 0.50 ILE (LSB) DLE (LSB) 4095 INTEGRAL LINEARITY ERROR vs CODE (2.
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TYPICAL CHARACTERISTICS (Cont.) TA = +25°C, VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted. INTERNAL REFERENCE vs TEMPERATURE 2.51875 1.0 2.51250 Internal Reference (V) Delta from 25°C (LSB) CHANGE IN GAIN vs TEMPERATURE 1.5 0.5 0.0 –0.5 –1.0 2.50625 2.50000 2.49375 2.48750 –1.5 2.
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THEORY OF OPERATION internal +2.5V reference will provide full dynamic range for a 0V to +VDD analog input. The ADS7828 is a classic Successive Approximation Register (SAR) A/D converter. The architecture is based on capacitive redistribution which inherently includes a sampleand-hold function. The converter is fabricated on a 0.6µ CMOS process. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced.
PAGE 10
must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. The following bus protocol has been defined (as shown in Figure 2): • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH.
PAGE 11
ADDRESS BYTE COMMAND BYTE MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB 1 0 0 1 0 A1 A0 R/W SD C2 C1 C0 PD1 PD0 X X The address byte is the first byte received following the START condition from the master device. The first five bits (MSBs) of the slave address are factory pre-set to 10010. The next two bits of the address byte are the device select bits, A1 and A0. Input pins (A1-A0) on the ADS7828 determine these two bits of the device address for a particular ADS7828.
PAGE 12
INITIATING CONVERSION MSB Provided the master has write-addressed it, the ADS7828 turns on the A/D converter’s section and begins conversions when it receives BIT 4 of the command byte shown in the Command Byte. If the command byte is correct, the ADS7828 will return an ACK condition.
PAGE 13
READING IN HS MODE See Figure 4 for a typical read sequence for HS mode. Included in the read sequence is the shift from F/S to HS modes. It may be desirable to remain in HS mode after reading a conversion; to do this, issue a repeated START instead of a STOP at the end of the read sequence, since a STOP causes the part to return to F/S mode. High Speed (HS) mode is fast enough that codes can be read out one at a time.
PAGE 14
READING WITH REFERENCE ON/OFF Internal VREF vs Turn-On Time Typical Characteristic plot. If the PD1 bit has been set to logic ‘0’ while using the ADS7828, then the settling time must be reconsidered after PD1 is set to logic ‘1’. In other words, whenever the internal reference is turned on after it has been turned off, the settling time must be long enough to get 12-bit accuracy conversion. The internal reference defaults to off when the ADS7828 power is on.
PAGE 15
LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7828 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an “n-bit” SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.com (3) 28-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7828E/250 TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS7828E/2K5 TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS7828EB/250 TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7828E/250 TSSOP PW 16 250 210.0 185.0 35.0 ADS7828E/2K5 TSSOP PW 16 2500 367.0 367.0 35.0 ADS7828EB/250 TSSOP PW 16 250 210.0 185.0 35.0 ADS7828EB/2K5 TSSOP PW 16 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.