Datasheet
www.ti.com
www.ti.com
ADS7826
ADS7827
ADS7829
SLAS388–JUNE 2003
Table 1. Timing Specifications (V
CC
= 2.7 V and Above -40°C to 85°C
SYMBOL DESCRIPTION MIN TYP MAX UNIT
t
SAMPLE
Analog input sample time 1.5 2.0 DCLOCK
Cycles
t
CONV
Conversion time ADS7829I or ADS7829IB 12 DCLOCK
Cycles
ADS7826I 11
ADS7827I 9
t
CYC
Cycle time ADS7829I or ADS7829IB 16 DCLOCK
Cycles
ADS7826 14
ADS7827 12
t
CSD
CS falling to DCLOCK LOW 0 ns
t
SU(CS)
CS falling to DCLOCK rising 30 ns
t
h(DO)
DCLOCK falling to current D
OUT
not valid 15 ns
t
d(DO)
DCLOCK falling to next D
OUT
valid 130 200 ns
t
dis
CS rising to D
OUT
3-state 40 80 ns
t
en
DCLOCK falling to D
OUT
enabled 75 175 ns
t
f
D
OUT
fall time 90 200 ns
t
r
D
OUT
rise time 110 220 ns
A falling CS signal initiates the conversion and data
DATA FORMAT
transfer. The first 1.5 to 2.0 clock periods of the
conversion cycle are used to sample the input signal.
The output data from the ADS7826/27/29 family is in
After the second falling DCLOCK edge, D
OUT
is
straight binary format. ADS7829 out is shown in
enabled and outputs a LOW value for one clock
Table 2, as an example. This table represents the
period. For the next N (N is 12 for ADS7829, 10 for
ideal output code for the given input voltage and does
ADS7826, and 8 for ADS7827) DCLOCK periods,
not include the effects of offset, gain error, or noise.
D
OUT
outputs the conversion result, most significant
For ADS7826 the last two LSB’s are don’t cares,
bit first. After the least significant bit has been sent,
while for ADS7827 the last four LSB’s are don’t
D
OUT
goes to 3-state after the rising edge of CS. A
cares.
new conversion is initiated only when CS has been
taken high and returned low again.
Table 2. Ideal Input Voltages and Output Codes (ADS7829 Shown as an Example)
DESCRIPTION ANALOG VALUE DIGITAL OUTPUT
FULL SCALE RANGE V
ref
STRAIGHT BINARY
LEAST SIGNIFICANT BIT (LSB) V
ref
/4096 BINARY CODE HEX CODE
Full scale V
ref
- 1 LSB 1111 1111 1111 FFF
Midscale V
ref
/2 1000 0000 0000 800
Midscale - 1 LSB V
ref
/2 - 1 LSB 0111 1111 1111 7FF
Zero 0 V 0000 0000 0000 000
15