Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal VSSOP 8

ADS7834

DESCRIPTION

The ADS7834 is a 12-bit sampling analog-to-digital converter

(A/D) complete with sample/hold, internal 2.5V reference,

and synchronous serial interface. Typical power dissipation

is 11mW at a 500kHz throughput rate. The device can be

placed into a power-down mode that reduces dissipation to

just 2.5mW. The input range is zero to the reference voltage,

and the internal reference can be overdriven by an external

voltage.

Low power, small size, and high speed make the ADS7834

ideal for battery-operated systems such as wireless

communication devices, portable multi-channel data loggers,

and spectrum analyzers. The serial interface also provides

low-cost isolation for remote data acquisition. The ADS7834

is available in a plastic mini-DIP-8 or an MSOP-8 package

and is ensured over the –40°C to +85°C temperature range.

12-Bit High-Speed, Low-Power Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 500kHz THROUGHPUT RATE

● 2.5V INTERNAL REFERENCE

● LOW POWER: 11mW

● SINGLE-SUPPLY +5V OPERATION

● DIFFERENTIAL INPUT

● SERIAL INTERFACE

● 12-BITS NO MISSING CODES

● MINI-DIP-8 AND MSOP-8

● 0V TO V

REF

INPUT RANGE

APPLICATIONS

● BATTERY-OPERATED SYSTEMS

● DIGITAL SIGNAL PROCESSING

● HIGH-SPEED DATA ACQUISITION

● WIRELESS COMMUNICATION SYSTEMS

SAR

CLK

Serial

Interface

Comparator

S/H Amp

DATA

+In

–In

CDAC

Internal

+2.5V Ref

Buffer

REF

CONV

10kΩ ±30%

SBAS098A – JANUARY 1998 – REVISED SEPTEMBER 2003

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (21 pages)

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ADS 783 ADS7834 4 SBAS098A – JANUARY 1998 – REVISED SEPTEMBER 2003 12-Bit High-Speed, Low-Power Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● ● ● ● ● The ADS7834 is a 12-bit sampling analog-to-digital converter (A/D) complete with sample/hold, internal 2.5V reference, and synchronous serial interface. Typical power dissipation is 11mW at a 500kHz throughput rate. The device can be placed into a power-down mode that reduces dissipation to just 2.5mW.
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PACKAGE/ORDERING INFORMATION PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) MAXIMUM DIFFERENTIAL LINEARITY ERROR (LSB) ±2 N/S(3) MSOP-8 " " " ±1 ±1 " " ±2 ±1 N/S(3) ±1 ADS7834E ADS7834E ADS7834EB ADS7834EB ADS7834P ADS7834PB SPECIFIED TEMPERATURE RANGE PACKAGE MARKING(2) ORDERING NUMBER(3) TRANSPORT MEDIA, QUANTITY DGK –40°C to +85°C C34 " " " MSOP-8 DGK –40°C to +85°C C34 " " " " Plastic DIP-8 P –40°C to +85°C " " " ADS7834P ADS7834PB ADS7834E/250 ADS7834E/2K5 ADS7
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SPECIFICATIONS At TA = –40°C to +85°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, internal reference, unless otherwise specified. ADS7834P, E PARAMETER ANALOG INPUT Full-Scale Input Span(1) Absolute Input Range CONDITIONS MIN +IN – (–IN) +IN –IN 0 –0.2 –0.
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TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified. OFFSET VOLTAGE vs TEMPERATURE 0.5 0 0.4 –1 Delta from +25°C (LSB) Delta from +25°C (LSB) FULL-SCALE ERROR vs TEMPERATURE 1 –2 –3 –4 –5 –6 0.3 0.2 0.1 0 –0.1 –0.2 –7 –8 –0.3 –40 –20 0 20 40 60 80 100 –40 –20 0 Temperature (°C) 2.3 460 2.2 450 440 430 420 410 2.1 100 2.0 1.9 1.8 –20 0 20 40 60 80 fSAMPLE = 125kHz 1.
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TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified. OFFSET VOLTAGE vs EXTERNAL REFERENCE VOLTAGE 0.300 0.2 0.200 0.1 Delta from VREF = 2.5V (mV) Delta from VREF = 2.5V (mV) FULL-SCALE ERROR vs EXTERNAL REFERENCE VOLTAGE 0.100 0.000 –0.100 –0.200 –0.300 –0.400 –0.500 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –0.600 –0.8 2.0 2.1 2.2 2.3 2.4 2.5 2.0 2.
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TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified. SIGNAL-TO-NOISE RATIO and SIGNAL-TO-(NOISE+DISTORTION) vs INPUT FREQUENCY FREQUENCY SPECTRUM (4096 Point FFT; fIN = 99.7kHz, –0.2dB) 76 0.
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THEORY OF OPERATION are common to both inputs. Thus, the –IN input is best used to sense a remote ground point near the source of the +IN signal. If the source driving the +IN signal is nearby, the –IN should be connected directly to ground. The ADS7834 is a high-speed. successive approximation register (SAR) analog-to-digital converter (A/D) with an internal 2.5V bandgap reference. The architecture is based on capacitive redistribution which inherently includes a sample/hold function.
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internal reference. This reference can be used to supply a small amount of source current to an external load, but the load should be static. Due to the internal 10kΩ resistor, a dynamic load will cause variations in the reference voltage, and will dramatically affect the conversion result. Note that even a static load will reduce the internal reference voltage seen at the buffer input. The amount of reduction depends on the load and the actual value of the internal “10kΩ” resistor.
PAGE 9
Figure 4 shows the typical method for placing the A/D into the power-down mode. If CONV is kept LOW during the conversion and is LOW at the start of the 13 clock cycle, then the device enters the power-down mode. It remains in this mode until the rising edge of CONV. Note that CONV must be HIGH for at least tACQ in order to sample the signal properly as well as to power-up the internal nodes.
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CONV 1 CLK 2 D11 (MSB) DATA 3 12 D10 D1 13 D0 (LSB) tACQ tCVSP SAMPLE/HOLD SAMPLE MODE HOLD SAMPLE HOLD (3) INTERNAL CONVERSION STATE IDLE POWER MODE CONVERSION IN PROGRESS IDLE tCKPD tCVPU FULL POWER LOW POWER (1) FULL POWER (2) NOTES: (1) The low power mode (“power-down”) is entered when CONV remains LOW during the conversion and is still LOW at the start of the 13th clock cycle. (2) The low power mode is exited when CONV goes HIGH.
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Table II offers a look at the two different modes of operation and the difference in power consumption. fSAMPLE POWER WITH CLK = 16 • fSAMPLE POWER WITH CLK = 8MHz 500kHz 11mW 11mW 250kHz 10mW 7mW 100kHz 9mW 4mW the conversion will terminate immediately, before all 12 bits have been decided. This can be a very useful feature when a resolution of 12 bits is not needed. An example would be when the converter is being used to monitor an input voltage until some condition is met.
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microcontrollers form various manufacturers. CONV would be tied to a general purpose I/O pin (SPI) or to a PCX pin (QSPI), CLK would be tied to the serial clock, and DATA would be tied to the serial input data pin such as MISO (master in slave out). FS = Full-Scale Voltage = VREF 1 LSB = FS/4096 1 LSB 11...111 Note the time tDRP shown in Figure 9. This represents the maximum amount of time between CONV going LOW and the start of the conversion clock.
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With this in mind, power to the ADS7834 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor is recommended. If needed, an even larger capacitor and a 5Ω or 10Ω series resistor my be used to lowpass filter a noisy supply. The ADS7834 draws very little current from an external reference on average as the reference voltage is internally buffered.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS7834E/250 VSSOP DGK 8 ADS7834EB/250 VSSOP DGK ADS7834EB/2K5 VSSOP DGK SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7834E/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7834EB/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS7834EB/2K5 VSSOP DGK 8 2500 367.0 367.0 35.
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