Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SSOP 28

12-Bit, 4-Channel Parallel Output Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● SINGLE SUPPLY: 2.7V to 5V

● 4-CHANNEL INPUT MULTIPLEXER

● UP TO 200kHz SAMPLING RATE

● FULL 12-BIT PARALLEL INTERFACE

● ±1LSB INL AND DNL

● NO MISSING CODES

● 72dB SINAD

● LOW POWER: 2mW

● SSOP-28 PACKAGE

DESCRIPTION

The ADS7842 is a complete, 4-channel, 12-bit Analog-to-

Digital Converter (ADC). It contains a 12-bit, capacitor-

based, Successive Approximation Register (SAR) ADC with

a sample-and-hold amplifier, interface for microprocessor

use, and parallel, 3-state output drivers. The ADS7842 is

specified at a 200kHz sampling rate while dissipating only

2mW of power. The reference voltage can be varied from

100mV to V

with a corresponding LSB resolution from

24µV to 1.22mV. The ADS7842 is tested down to 2.7V

operation.

Low power, high speed, and an onboard multiplexer make

the ADS7842 ideal for battery-operated systems such as

portable, multi-channel dataloggers and measurement equip-

ment. The ADS7842 is available in an SSOP-28 package

and is tested over the –40°C to +85°C temperature range.

APPLICATIONS

● DATA ACQUISITION

● TEST AND MEASUREMENT

● INDUSTRIAL PROCESS CONTROL

● MEDICAL INSTRUMENTS

● LABORATORY EQUIPMENT

SAR

Output

Latches

and

3-State

Drivers

3-State

Parallel

Data Bus

Comparator

ADS7842

BUSY

CLK

CDAC

REF

4-Channel

MUX

AIN2

AIN1

AIN0

AIN3

ADS7842

SBAS103C – SEPTEMBER 2000 – REVISED OCTOBER 2006

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (20 pages)

PAGE 1
ADS7842 ADS 784 2 SBAS103C – SEPTEMBER 2000 – REVISED OCTOBER 2006 12-Bit, 4-Channel Parallel Output Sampling ANALOG-TO-DIGITAL CONVERTER DESCRIPTION FEATURES ● SINGLE SUPPLY: 2.7V to 5V The ADS7842 is a complete, 4-channel, 12-bit Analog-toDigital Converter (ADC). It contains a 12-bit, capacitorbased, Successive Approximation Register (SAR) ADC with a sample-and-hold amplifier, interface for microprocessor use, and parallel, 3-state output drivers.
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PACKAGE/ORDERING INFORMATION PRODUCT MINIMUM RELATIVE ACCURACY (LSB) SINAD (dB) ADS7842E ±2 " " ADS7842EB " PACKAGE-LEAD PACKAGE DESIGNATOR(1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY 68 SSOP-28 DB –40°C to +85°C ADS7842E " " " " " ADS7842E ADS7842E/1K Rails, 48 Tape and Reel, 1000 ±1 70 SSOP-28 DB –40°C to +85°C ADS7842EB " " " " " " ADS7842EB ADS7842EB/1K Rails, 48 Tape and Reel, 1000 NOTE: (1) For the most current speci
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ELECTRICAL CHARACTERISTICS: +5V At TA = –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted. ADS7842E PARAMETER CONDITIONS MIN TYP RESOLUTION 0 VREF 0.15 0.1 30 70 ✻ ✻ ✻ ✻ 10kHz 10kHz 10kHz 50kHz –78 71 79 120 68 72 0.1 5 40 2.5 0.001 –72 70 76 3.0 –0.3 3.5 –80 72 81 ✻ ✻ ✻ ✻ ✻ ✻ 100 3 ±1 ±1 ✻ ✻ ±3 ✻ 5.5 +0.8 ✻ ✻ ✻ 4.75 550 300 –40 dB dB dB dB ✻ V GΩ µA µA µA ✻ ✻ ✻ V V V V ✻ MHz ✻ ✻ ✻ ✻ V µA µA µA mW ✻ °C ✻ 3.
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ELECTRICAL CHARACTERISTICS: +2.7V At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. ADS7842E PARAMETER CONDITIONS MIN TYP RESOLUTION 0 Channel-to-Channel Isolation REFERENCE INPUT Range Resistance Input Current POWER-SUPPLY REQUIREMENTS +VCC Quiescent Current ±0.8 0.15 0.1 30 70 ±2 ±0.5 ±5 1.0 ±4 1.
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TYPICAL CHARACTERISTICS: +5V At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 • fSAMPLE = 3.2MHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 10.3kHz, –0.
PAGE 6
TYPICAL CHARACTERISTICS: +2.7V At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 10.6kHz, –0.2dB) 0 0 –20 –20 –40 –40 Amplitude (dB) –60 –80 –60 –80 –100 –100 –120 –120 0 15.6 31.3 46.9 0 62.5 62.5 SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 90 –90 85 74 –85 SFDR 70 SFDR (dB) SNR and SINAD (dB) 46.
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TYPICAL CHARACTERISTICS: +2.7V (Continued) At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted. POWER-DOWN SUPPLY CURRENT vs TEMPERATURE 400 140 350 120 Supply Current (nA) Supply Current (µA) SUPPLY CURRENT vs TEMPERATURE 300 250 200 150 100 80 60 40 100 20 –40 –20 0 20 40 60 80 100 –40 –20 0 40 60 80 100 DIFFERENTIAL LINEARITY ERROR vs CODE 1.00 1.00 0.75 0.75 0.50 0.
PAGE 8
TYPICAL CHARACTERISTICS: +2.7V (Continued) At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 • fSAMPLE = 2MHz, unless otherwise noted.
PAGE 9
THEORY OF OPERATION some operating modes. While the converter is in the hold mode, or after the sampling capacitor has been fully charged, the input impedance of the analog input is greater than 1GΩ. The ADS7842 is a classic SAR ADC. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µm CMOS process. EXTERNAL CLOCK The ADS7842 requires an external clock to run the conversion process.
PAGE 10
STARTING A CONVERSION SYMBOL DESCRIPTION tCONV tACQ tCKP tCKL tCKH t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Conversion Time Acquisition Time Clock Period Clock LOW Clock HIGH CS to WR/RD Setup Time Address to CS Hold Time CS LOW CLK to WR Setup Time CS to BUSY LOW CLK to WR LOW CLK to WR HIGH WR to CLK HIGH Address Hold Time Address Setup Time BUSY to RD Delay CLK LOW to BUSY HIGH BUS Access BUS Relinquish Address to RD HIGH Address Hold Time RD HIGH to CLK LOW A conversion is initiat
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CS WR BUSY A0 A1 COMMENTS 0 RD X 1 1 X Power-Down Mode 0 X 1 0 X Wake-Up Mode DIGITAL OUTPUT STRAIGHT BINARY DESCRIPTION ANALOG INPUT Least Significant Bit (LSB) Full-Scale Midscale Midscale –1LSB Zero Full-Scale means rising edge triggered. X = Don't care. TABLE III. Truth Table for Power-Down and Wake-Up Modes. 1.2207mV 4.99878V 2.5V 2.49878V 0V BINARY CODE 1111 1000 0111 0000 1111 0000 1111 0000 HEX CODE 1111 0000 1111 0000 FFF 800 7FF 000 TABLE IV.
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CS t1 t3 RD CLK t12 t11 BUSY n–1 Conversion n To prevent PWD A0 must be 0 A0 t13 DB0-DB11 t14 n-1 DATA VALID NOTE: Internal register of current conversion updated 1/2 clock cycle prior to BUSY going HIGH. FIGURE 4. Read Timing Following a Conversion. CS t2 t1 t3 RD CLK t12 t11 BUSY t15 t16 A0 NOTE: Rising edge of RD while A0 = 1 initiates power down immediately. FIGURE 5. Entering Power-Down Using RD and A0.
PAGE 13
LAYOUT REFERENCE INPUT The external reference sets the analog input range. The ADS7842 will operate with a reference in the range of 100mV to +VCC. There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB size and is equal to the reference voltage divided by 4096.
PAGE 14
Revision History DATE REVISION PAGE SECTION DESCRIPTION 10/06 C 4 Electrical Characteristics Dynamic Characteristics—total harmonic distortion: added new conditions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 14 ADS7842 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7842E/1K SSOP DB 28 1000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 ADS7842EB/1K SSOP DB 28 1000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7842E/1K SSOP DB 28 1000 367.0 367.0 38.0 ADS7842EB/1K SSOP DB 28 1000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.