ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 Dual, 2MSPS, 12-Bit, 2 + 2 or 3 + 3 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS7863 FEATURES DESCRIPTION • • • The ADS7863 is a dual, 12-bit, 2MSPS, analog-to-digital converter (ADC) with four fully differential or six pseudo-differential input channels grouped into two pairs for high-speed, simultaneous signal acquisition.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range, unless otherwise noted. ADS7863 PARAMETER Supply voltage, AVDD to AGND Supply voltage, BVDD to BGND MIN NOM MAX 2.7 5.0 5.5 Low voltage levels 2.7 5V logic levels 4.5 5.0 5.5 0.5 2.5 2.525 Reference input voltage on REFIN Analog differential input voltage (CHXX+) – (CHXX–) Operating ambient temperature range, TA UNIT V 3.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS At TA = –40°C to +125°C, entire power-supply range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +125°C, entire power-supply range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.
ADS7863 www.ti.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com TIMING CHARACTERISTICS (continued) CLOCK Cycle 1 Cycle 2 10ns 10ns 5ns CONVST A 5ns B C NOTE: All CONVST commands that occur more than 10ns before the rising edge of cycle ‘1’ of the external clock (Region ‘A’) initiate a conversion on the rising edge of cycle ‘1’.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS Over entire supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted. INTEGRAL NONLINEARITY vs DATA RATE INTEGRAL NONLINEARITY vs TEMPERATURE 1.0 1.00 0.8 0.75 0.6 0.50 0.2 INL (LSB) INL (LSB) Positive Positive 0.4 0 -0.2 Negative 0.25 0 -0.25 Negative -0.4 -0.50 -0.6 -0.75 -0.8 -1.0 0.50 0.75 1.00 1.25 1.50 1.75 -1.00 -40 -25 -10 2.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over entire supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted. OFFSET ERROR AND OFFSET MATCH vs ANALOG SUPPLY VOLTAGE OFFSET ERROR AND OFFSET MATCH vs TEMPERATURE 2.0 0.8 Offset and Offset Match (LSB) Offset and Offset Match (LSB) 1.0 0.6 0.4 0.2 Offset Match 0 -0.2 Offset -0.4 -0.6 -0.8 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 1.0 Offset Match 0.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) Over entire supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 100kHz, fSAMPLE = 1.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Over entire supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted. TOTAL HARMONIC DISTORTION vs INPUT SIGNAL FREQUENCY TOTAL HARMONIC DISTORTION vs TEMPERATURE -78 -76 -78 AVDD = 5V -80 AVDD = 2.7V -82 AVDD = 2.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) Over entire supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and tDATA = 2MSPS, unless otherwise noted. ANALOG SUPPLY CURRENT vs DATA RATE (Auto-NAP Mode) ANALOG SUPPLY CURRENT vs TEMPERATURE (Auto-NAP Mode) 6 1.4 1.2 5 AVDD = 5V Reference ON 1.0 AVDD (mA) AVDD (mA) 4 3 Reference OFF AVDD = 2.7V 0.8 0.6 2 0.4 1 0.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com APPLICATIONS INFORMATION GENERAL DESCRIPTION CHx1+ The ADS7863 includes two 12-bit analog-to-digital converters (ADCs) that operate based on the successive-approximation register (SAR) principle. The ADCs sample and convert simultaneously. Conversion time can be as low as 406.25ns. Adding the acquisition time of 62.5ns and an additional clock cycle for setup/hold time requirements and skew results in a maximum conversion rate of 2MSPS.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 The minimum –3dB bandwidth of the driving operational amplifier can be calculated as shown in Equation 1, with n = 12 being the resolution of the ADS7863: ln(2) ´ (n + 1) f-3dB = 2p ´ tACQ (1) With tACQ = 62.5ns, the minimum bandwidth of the driving amplifier is 23MHz. The required bandwidth can be lower if the application allows a longer acquisition time.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com RESET The ADS7863 features an internal power-on-reset (POR) function. When the device is powered up, the POR sets the device in default mode when the AVDD reaches 1.8V. An external software reset can be issued using SDI register bits A[2:0] (see the Digital section). REFIN The reference input is not buffered and is directly connected to the ADC. The converter generates spikes on the reference input voltage because of internal switching.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 DIGITAL DP: Deep power-down enable ('1' = device in deep power-down mode) N: Nap power-down enable ('1' = device in Nap power-down mode) AN: AutoNap power-down enable ('1' = device in AutoNap power-down mode) RP: Reference power-down ('1' = reference turned off) S4: Special read mode for Modes II and IV ('1' = special mode enabled) This section addresses the timing and control of the ADS7863 serial interface.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com Serial Data Output (SDOx) Converted data on the SDOx pins become valid with the third falling CLOCK edge after generating an RD pulse. The following sections explain the different modes of operation in detail. The digital output code format of the ADS7863 is binary twos complement, as shown in Table 9. Conversion results can be read out multiple times until a new conversion is issued from the CONVST input.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 MODE I With the M0 and M1 pins both set to '0', the ADS7863 enters manual channel control operation and outputs data on both SDOA and SDOB, respectively. The SDI pin switches between the channels. A conversion is initiated by bringing CONVST high. 16 clock cycles are required to perform a single conversion. With the rising edge of CONVST, the ADS7863 switches asynchronously to the external CLOCK from sample to hold mode.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com MODE II from both ADCs (instead of 16 cycles, if M1 = '0'), the ADS7863 requires 1.0ms to perform a complete conversion/read cycle. If the CONVST signal is issued every 0.5ms (required for the RD signal) as in Mode I, every second pulse is ignored; see Figure 33. With M0 = '0' and M1 set to '1', the ADS7863 also operates in manual channel control mode and outputs data on the SDOA pin only while SDOB is set to 3-state.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 MODE III Output data consist of a channel indicator ('0' for CHx0 or '1' for CHx1), followed by a '0', 12 bits of conversion results, and another '00'. With M0 set to '1' and M1 = '0', the ADS7863 automatically cycles between the differential inputs (ignoring the SDI register bits C[1:0]) while offering the conversion result of CHAx on SDOA and the conversion result of CHBx on SDOB (see Figure 34).
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com MODE IV In the same way as Mode II, Mode IV uses the SDOA output line exclusively to transmit data while the differential channels are switched automatically. Following the first conversion after M1 goes high, the SDOB output 3-states (see Figure 35). 16 1 1 Output data consist of a channel indicator ('0' for CHx0 or '1' for CHx1), followed by the ADC indicator ('0' for CHAx or '1' for CHBx), 12 bits of conversion results, and end with '00'.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 SPECIAL MODE II (Not ADS7861-Compatible) For Mode II, a special read mode is available in the ADS7863 where both data results can be read out, triggered by a single RD pulse. To activate this mode, bit S4 in the SDI Register must be set to '1' (see also the Serial Data Input section). 16 1 1 16 1 The CONVST and RD pins can remain tied together, but do not need to be issued every 16 CLOCK cycles.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com SPECIAL MODE IV (Not ADS7861-Compatible) Analogous to Special Mode II, the ADS7863 also offers a special read mode for Mode IV in which both data results of a conversion can be read, triggered by a single RD pulse. In this case as well, bit S4 in the SDI register must be set to '1' while the CONVST and RD pins can still be tied together . 16 1 1 16 1 As with Special Mode II, these two pins do not need to be issued every 16 CLOCK cycles.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 PSEUDO-DIFFERENTIAL MODE I (Not ADS7861-Compatible) In Mode I, the ADS7863 input multiplexers can also operate in a pseudo-differential manner. In this case, SDI bits C[1:0] are used to choose the channels accordingly. 16 1 1 16 1 For more details, see the Serial Data Input section. Data are available on both output terminals, SDOA and SDOB. The input multiplexer cannot be used for pseudo-differential signals in Mode III or Mode IV.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com PSEUDO-DIFFERENTIAL MODE II (Not ADS7861-Compatible) Channel switching is performed by setting the C[1:0] bits in the SDI Register accordingly (see also the Serial Data Input section). In Mode II, the ADS7863 input multiplexers can also operate in a pseudo-differential configuration. In this case, output data are available on terminal SDOA only, while SDOB is held in 3-state.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 Programming the Reference DAC (Not ADS7861-Compatible) The internal reference DAC can be set by issuing an RD pulse while providing an SDI word with P[1:0] = '01' and A[2:0] = '001'. Thereafter, a second RD pulse must be generated with an SDI word starting with the first two bits being ignored, followed by the actual 10-bit DAC value (see Figure 40).
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com Power-Down Modes and Reset (Not ADS7861-Compatible) The ADS7863 has a comprehensive built-in power-down feature. There are three power-down modes: deep power-down, nap power-down, and auto-nap power-down. All three power-down modes are activated with the 12th falling CLOCK edge of the SDI access, during which the related bit asserts (DP = '1', N = '1', or AN = '1').
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 ADS7861 COMPATIBILITY REFIN The ADS7863IDBQ is pin-compatible with the ADS7861E/EB/EG4. However, there are some differences between the two devices that must be considered when migrating from the ADS7861 to the ADS7863 in an existing design. The ADS7863 offers an unbuffered REFIN input with a code-dependent input impedance while featuring a programmable and buffered reference output (REFOUT).
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com APPLICATION INFORMATION fFILTER = The absolute minimum configuration of the ADS7863 is shown in Figure 41. In this case, the ADS7863 is used in dual-channel mode only, with the default settings of the device after power up. ln(2) ´ (n + 1) 2´p´2´R´C (3) It is recommended to use a capacitor value of at least 20pF.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7863 circuitry. This condition is particularly true if the CLOCK input is approaching the maximum throughput rate. In this case, it is recommended to have a fixed phase relationship between CLOCK and CONVST.
ADS7863 SBAS383E – JUNE 2007 – REVISED JANUARY 2011 www.ti.com Figure 42.
ADS7863 www.ti.com SBAS383E – JUNE 2007 – REVISED JANUARY 2011 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (April 2010) to Revision E • Page Changed DC Accuracy, GERR maximum specification in ELectrical Characteristics table ................................................... 4 Changes from Revision C (April 2009) to Revision D Page • Deleted footnote 2 from Electrical Characteristics ........................
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7863IDBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 ADS7863IRGER VQFN RGE 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS7863IRGET VQFN RGE 24 250 180.0 12.4 4.3 4.3 1.5 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7863IDBQR SSOP DBQ 24 2500 367.0 367.0 38.0 ADS7863IRGER VQFN RGE 24 3000 338.1 338.1 20.6 ADS7863IRGET VQFN RGE 24 250 210.0 185.0 35.
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