Datasheet

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BIPOLAR INPUTS
EXPLANATION OF CLOCK, RESET AND
R
1
R
2
+IN
−
IN
REF
OUT
(pin 33)
2.5V
4k
Ω
20k
Ω
Bipolar Input
BIPOLAR INPUT R
1
R
2
±
10V 1k
Ω
5k
Ω
±
5V 2k
Ω
10k
Ω
±
2.5V 4k
Ω
20k
Ω
OPA340
ADS7864
TIMING AND CONTROL
CLOCK
HOLDA
HOLDB
HOLDC
RESET
t
9
t
1
t
6
t
8
t
2
t
3
t
5
t
7
THEORY OF OPERATION
START OF A CONVERSION
ADS7864
SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005
Hold signals. The FIFO mode will allow the six
registers to be used by a single channel pair, and
The differential inputs of the ADS7864 were designed
therefore three locations for CH X0 and three lo-
to accept bipolar inputs (–V
REF
and +V
REF
) around the
cations for CH X1 can be acquired before they are
internal reference voltage (2.5V), which corresponds
read from the part.
to a 0V to 5V input range with a 2.5V reference. By
using a simple op amp circuit featuring a single
amplifier and four external resistors, the ADS7864
BUSY PINS
can be configured to accept bipolar inputs. The
conventional ±2.5V, ±5V, and ±10V input ranges can
CLOCK—An external clock has to be provided for the
be interfaced to the ADS7864 using the resistor
ADS7864. The maximum clock frequency is 8MHz.
values shown in Figure 25 .
The minimum clock cycle is 125ns (see Figure 26 , t
5
),
and the clock has to remain high (see Figure 26 , t
6
)
or low (see Figure 26 , t
7
) for at least 40ns.
Figure 25. Level Shift Circuit for Bipolar Input
Ranges
The ADS7864 uses an external clock (CLOCK, pin
Figure 26. Start of the Conversion
22) which controls the conversion rate of the CDAC.
With an 8MHz external clock, the A/D sampling rate
RESET—Bringing reset low will reset the ADS7864. It
is 500kHz which corresponds to a 2µs maximum
will clear all the output registers, stop any actual
throughput time.
conversions and will close the sampling switches.
Reset has to stay low for at least 20ns (see Fig-
ure 26 , t
8
). The reset should be back high for at least
20ns (see Figure 26 , t
9
), before starting the next
The ADS7864 contains two 12-bit A/D converters that
conversion (negative hold edge).
operate simultaneously. The three hold signals
BUSY—Busy goes low when the internal A/D con-
( HOLDA, HOLDB, HOLDC) select the input MUX and
verters start a new conversion. It stays low as long as
initiate the conversion. A simultaneous hold on all six
the conversion is in progress (see Figure 27 , 13
channels can occur with all three hold signals strobed
clock-cycles, t
10
) and rises again after the data is
together. The converted values are saved in six
latched to the output register. With Busy going high,
registers. For each read operation the ADS7864
the new data can be read. It takes at least 16 clock
outputs 16 bits of information (12 Data, 3 Channel
cycles (see Figure 27 , t
11
) to complete conversion.
Address and Data Valid). The Address/Mode signals
(A0, A1, A2) select how the data is read from the
ADS7864. These Address/Mode signals can define a
selection of a single channel, a cycle mode that
By bringing one or all of the HOLDX signals low, the
cycles through all channels or a FIFO mode that
input data of the corresponding channel X is immedi-
sequences the data determined by the order of the
ately placed in the hold mode (5ns). The conversion
of this channel X follows as soon as the A/D
converter is available for the particular channel. If
14