Datasheet

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ADS7864
SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005
other channels are already in the hold mode but not Once a particular hold signal goes low, further im-
converted, then the conversion of channel X is put in pulses of this hold signal are ignored until the
the queue until the previous conversion has been conversion is finished or the part is reset. When the
completed. If more than one channel goes into hold conversion is finished ( BUSY signal goes high), the
mode within one clock cycle, then channel A will be sampling switches will close and sample the selected
converted first if HOLDA is one of the triggered hold channel. The start of the next conversion must be
signals. Next, channel B will be converted, and last, delayed to allow the input capacitor of the ADS7864
channel C. If it is important to detect a hold command to be fully charged. This delay time depends on the
during a certain clock cycle, then the falling edge of driving amplifier, but should be at least 175ns
the hold signal has to occur at least 10ns before the (see Figure 27 , t
4
).
falling edge of the clock. (see Figure 26 , t
1
). The hold
The ADS7864 can also convert one channel continu-
signal can remain low without initiating a new conver-
ously, as it is shown in Figure 27 with channel B.
sion. The hold signal has to be high for at least 15ns
Therefore, HOLDA and HOLDC are kept high all the
(see Figure 26 , t
2
) before it is brought low again and
time. To gain acquisition time, the falling edge of
hold has to stay low for at least 20ns (see Figure 26 ,
HOLDB takes place just before the falling edge of
t
3
).
clock. One conversion requires 16 clock cycles. Here,
In the example of Figure 26 , the signal HOLDB goes data is read after the next conversion is initiated by
low first and channel B0 and B1 will be converted HOLDB. To read data from channel B, A1 is set high
first. The falling edges of HOLDA and HOLDC occur and A2 is low. As A0 is low during the first reading
within the same clock cycle. Therefore, the channels (A2 A1 A0 = 010) data B0 is put to the output. Before
A0 and A1 will be converted as soon as the channels the second RD, A0 switches high (A2 A1 A0 = 011)
B0 and B1 are finished (plus acquisition time). When so data from channel B1 is read.
the A-channels are finished, the C-channels will be
converted. The second HOLDA signal is ignored, as
the A-channels are not converted at this point in time.
Table 1. Timing Specifications
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
1
HOLD (A, B, C) before falling edge of clock 10 ns
t
2
HOLD high time to be recognized again 15 ns
t
3
HOLD low time 20 ns
t
4
Input capacitor charge time 175 ns
t
5
Clock period 125 ns
t
6
Clock high time 40 ns
t
7
Clock low time 40 ns
t
8
Reset pulse width 20 ns
t
9
First hold after reset 20 ns
t
10
Conversion time 12.5 × t
5
ns
t
11
Successive conversion time (16 × t
5
) 2 µs
t
12
Address setup before RD 10 ns
t
13
CS before end of RD 30 ns
t
14
RD high time 30 ns
15