Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 32

S/H

Comparator

CDAC

Input

MUX

REF

SAR

S/H

Comparator

CDAC

REF

OUT

AGND

SAR

10-BitDAC

2.5VReference

ParallelInterface

CHA0+

CHA0-

CHA1+

CHA1-

DB[11:0]

CLOCK

BUSY

CONVST

BGND

CHB0+

CHB0-

CHB1+

CHB1-

Input

MUX

ADS7865

www.ti.com

SBAS441C –OCTOBER 2008–REVISED APRIL 2012

Dual, 12-Bit, 3+3 or 2+2 Channel, Simultaneous Sampling

Analog-to-Digital Converter

Check for Samples: ADS7865

FEATURES

DESCRIPTION

The ADS7865 is a dual, 12-bit, 2MSPS analog-to-

• Six Pseudo- or Four Fully Differential Inputs

digital converter (ADC) with four fully differential or six

• SNR: 71.7dB, THD: –87dB

pseudo-differential input channels grouped into two

• Programmable Channel Sequencer

pairs for high-speed, simultaneous signal acquisition.

Inputs to the sample-and-hold (S/H) amplifiers are

• Programmable and Buffered Internal 2.5V

fully differential and are maintained differentially to

Reference

the input of the ADC. This architecture provides

• Flexible Power-Down Features

excellent common-mode rejection of 72dB at 100kHz,

• Variable Power-Supply Ranges: 2.7V to 5.5V

which is a critical performance characteristic in noisy

environments.

• Low-Power Operation: 44mW Maximum at 5V

• Operating Temperature Range:

The ADS7865 is pin-compatible with the ADS7862,

but offers additional features such as a

–40°C to +125°C

programmable channel sequencer and reference

• Pin-Compatible Upgrade for the ADS7862

output, flexible supply voltage (2.7V to 5.5V for AV

and BV

), a pseudo-differential input multiplexer with

APPLICATIONS

three channels per ADC, and several power-down

features.

• Motor Control

• Multi-Axis Positioning Systems

The ADS7865 is offered in a TQFP-32 package. It is

specified over the extended operating temperature

• Three-Phase Power Control

range of –40°C to +125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (32 pages)

PAGE 1
ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 Dual, 12-Bit, 3+3 or 2+2 Channel, Simultaneous Sampling Analog-to-Digital Converter Check for Samples: ADS7865 FEATURES DESCRIPTION • • • • The ADS7865 is a dual, 12-bit, 2MSPS analog-todigital converter (ADC) with four fully differential or six pseudo-differential input channels grouped into two pairs for high-speed, simultaneous signal acquisition.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS At TA = –40°C to +125°C; over entire power-supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +125°C; over entire power-supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted. ADS7865 PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT INTERNAL VOLTAGE REFERENCE Resolution Reference output DAC resolution 10 Over 20% to 100% DAC range 0.496 DAC = 0x3FF, –40°C < TA < +125°C 2.485 DAC = 0x3FF at +25°C 2.495 Bits 2.515 V 2.
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ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 ELECTRICAL CHARACTERISTICS (continued) At TA = –40°C to +125°C; over entire power-supply voltage range, VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted. ADS7865 PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT POWER SUPPLY AVDD Analog supply voltage AVDD to AGND 2.7 5.0 5.5 BVDD Buffer I/O supply current BVDD to BGND 2.7 3.0 5.5 V AVDD = 2.7V 4.1 6.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.
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ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 TERMINAL FUNCTIONS (continued) PIN NUMBER NAME 23 BGND Buffer I/O ground. Connect to digital ground plane. DESCRIPTION 24 BVDD Buffer I/O power supply, 2.7V to 5.5V. Decouple to BGND with a 1μF ceramic capacitor.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com TIMING REQUIREMENTS (1) ADS7865 PARAMETER TEST CONDITIONS MIN fCLOCK = 32MHz TYP MAX 13 UNIT tCONV Conversion time tACQ Acquisition time tCLK fCLK CLOCK frequency tCLK CLOCK period tCLKL CLOCK low time 9.4 ns tCLKH CLOCK high time 9.
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ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS Over the entire supply voltage range; VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted. INTEGRAL NONLINEARITY vs DATA RATE INTEGRAL NONLINEARITY vs TEMPERATURE 1.00 1.00 0.75 0.75 0.50 0.50 Positive 0.25 INL (LSB) INL (LSB) Positive 0 -0.25 0.25 0 -0.25 Negative Negative -0.50 -0.50 -0.75 -0.75 -1.00 0.50 0.75 1.00 1.25 1.50 1.75 -1.00 -40 -25 -10 2.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Over the entire supply voltage range; VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted. OFFSET ERROR AND OFFSET MATCH vs ANALOG SUPPLY VOLTAGE OFFSET ERROR AND OFFSET MATCH vs TEMPERATURE 2.0 0.8 Offset Error and Offset Match (LSB) Offset Error and Offset Match (LSB) 1.0 Offset Match 0.6 0.4 Offset Error 0.2 0 -0.2 -0.4 -0.6 -0.8 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.
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ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) Over the entire supply voltage range; VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 100kHz, fSAMPLE = 1.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Over the entire supply voltage range; VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted. TOTAL HARMONIC DISTORTION vs INPUT SIGNAL FREQUENCY TOTAL HARMONIC DISTORTION vs TEMPERATURE -78 -76 -78 -80 -80 THD (dB) THD (dB) -82 -82 AVDD = 5V -84 -86 -84 AVDD = 5V -86 AVDD = 2.7V -88 -88 AVDD = 2.
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ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 TYPICAL CHARACTERISTICS (continued) Over the entire supply voltage range; VREF = 2.5V (internal), fCLK = 32MHz, and fDATA = 2MSPS, unless otherwise noted. ANALOG SUPPLY CURRENT vs DATA RATE (Auto-NAP Mode) ANALOG SUPPLY CURRENT vs TEMPERATURE (Auto-NAP Mode) 6 1.8 1.6 5 1.4 AVDD (mA) AVDD (mA) 4 Reference ON 3 2 AVDD = 5V 1.2 1.0 AVDD = 2.7V 0.8 0.6 Reference OFF 0.4 1 0.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com APPLICATION INFORMATION GENERAL DESCRIPTION The ADS7865 includes two 12-bit analog-to-digital converters (ADCs) that operate based on the successive-approximation register (SAR) principle. The ADCs sample and convert simultaneously. Conversion time can be as low as 406.25ns. Adding the acquisition time of 62.5ns and an additional clock cycle for setup/hold time requirements and skew results in a maximum conversion rate of 2MSPS.
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ADS7865 www.ti.com The minimum –3dB bandwidth of the driving operational amplifier can be calculated as shown in Equation 1, with n = 12 being the resolution of the ADS7865: ln(2) ´ (n + 1) f-3dB = 2p ´ tACQ (1) With tACQ = 62.5ns, the minimum bandwidth of the driving amplifier is 23MHz. The required bandwidth can be lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill the settling requirement shown in Equation 1.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 RESET www.ti.com REFIN reference stable (see the previous discussion of REFIN). For applications that use an external reference source, the internal reference can be disabled using bit RP in the SDI Register (see the Digital section). The settling time of the REFOUT pin is 500μs (max) with the reference capacitor connected. The default value of the REFOUT pin after power-up is 2.5V.
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ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 DIGITAL This section reviews the timing and control of the ADS7865 parallel interface. Configuration Register The configuration register can be set by issuing a write access on the parallel interface. The data present on DB[11:0] are latched with the rising edge of WR. The data word width of the configuration register is 12 bits; its structure is shown in Table 4. The default value of this register after power-up is 0x000.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com Figure 32 shows a complete timing diagram consisting of a write access to set up the proper input channel, followed by an initiation of a conversion and the read access of both conversion results. The digital output code format of the ADS7865 is in binary twos complement, as shown in Table 8. Conversion results can be read out only once. A second read access (without issuing a new conversion) results in 000h as the output value.
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ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 Sequencer Register The ADS7865 features a programmable sequencer that controls the switching of the ADC input multiplexer. To set up the sequencer, two write accesses to the ADC are required. During the first write access, the programming of the sequencer must be enabled by setting R[1:0] = '01' and A[2:0] = '100' in the Configuration Register.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com Table 12. Channel Selection Table 13.
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ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 Programming the Reference DAC The internal reference DAC can be set by issuing a WR pulse while providing a control word with R[1:0] = '01' and A[2:0] = '001' (see Table 4). Thereafter, a second WR pulse must be generated with the data bus bits DB[11:10] = '00' and DB[9:0] containing the actual 10-bit DAC value, with DB9 being the MSB (see Figure 35).
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com Power-Down Modes and Reset The ADS7865 has a comprehensive built-in powerdown feature. There are three power-down modes: deep power-down, nap power-down, and auto-nap power-down. All three power-down modes are activated with the rising WR edge after having been activated by asserting the corresponding bit in the Configuration Register (DP = '1', N = '1', or AN = '1').
PAGE 23
ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 ADS7862 COMPATIBILITY The ADS7865IPBS is pin-compatible with the ADS7862Y. However, there are some differences between the two devices that must be considered when migrating from the ADS7862 to the ADS7865 in an existing design. WR versus A0 One of the differences is that pin 22, which triggers writing to the internal Configuration Register of the ADS7865 (WR), is used to select the input channel on the ADS7862 (A0).
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com APPLICATION INFORMATION fFILTER = ln(2) ´ (n + 1) 2´p´2´R´C (3) The absolute minimum configuration of the ADS7865 in an application is shown in Figure 36. In this case, the ADS7865 is used in dual-channel mode only, with the default settings of the device after power up. It is recommended to use a capacitor value of at least 20pF.
PAGE 25
ADS7865 www.ti.com LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7865 circuitry. This caution is particularly true if the CLOCK input approaches the maximum throughput rate. In this case, it is recommended to have a fixed phase relationship between CLOCK and CONVST.
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ADS7865 SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 www.ti.com Top View ADS7865I 32 470 nF 1.0 mF to AV DD 0.1 mF 31 30 29 28 27 26 25 REFIN BVDD REFOUT BGND AGND 22 AV DD 21 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 0.1 mF 1 mF to BVDD 16 LEGEND TOP layer; copper pour and traces lower layer; AGND area lower layer; BGND area via Figure 37.
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ADS7865 www.ti.com SBAS441C – OCTOBER 2008 – REVISED APRIL 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (May 2010) to Revision C • Page Deleted Ordering Information table .......................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS7865IPBSR Package Package Pins Type Drawing TQFP PBS 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 7.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.2 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7865IPBSR TQFP PBS 32 1000 367.0 367.0 38.
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