Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SOT 23 6

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FEATURES

APPLICATIONS

DESCRIPTION

CDAC

SAR

Conversion

and

Control

Logic

Comparator

12/10/8 BIT ADC

VIN

REF/V

SCLK

SDO

GND

S/H

ADS7866

ADS7867

ADS7868

SLAS465 – JUNE 2005

1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE

ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE

The sampling, conversion, and activation of digital

output SDO are initiated on the falling edge of CS.

• Single 1.2-V to 3.6-V Supply Operation

The serial clock SCLK is used for controlling the

• High Throughput

conversion rate and shifting data out of the converter.

Furthermore, SCLK provides a mechanism to allow

– 200/240/280KSPS for 12/10/8-Bit V

≥ 1.6 V

digital host processors to synchronize with the con-

– 100/120/140KSPS for 12/10/8-Bit V

≥ 1.2 V

verter. These converters interface with

• ± 1.5LSB INL, 12-Bit NMC (ADS7866)

micro-processors or DSPs through a high-speed SPI

• 71 dB SNR, –83 dB THD at f

= 30 kHz

compatible serial interface. There are no pipeline

delays associated with the device.

(ADS7866)

• Synchronized Conversion with SCLK

The minimum conversion time is determined by the

frequency of the serial clock input, SCLK, while the

• SPI Compatible Serial Interface

maximum frequency of SCLK is determined by the

• No Pipeline Delays

minimum sampling time required to charge the input

• Low Power

capacitance to 12/10/8-bit accuracy for the

ADS7866/67/68, respectively. The maximum

– 1.39 mW Typ at 200 KSPS, V

= 3.6 V

throughput is determined by how often a conversion

– 0.39 mW Typ at 200 KSPS, V

= 1.6 V

is initiated when the minimum sampling time is met

– 0.22 mW Typ at 100 KSPS, V

= 1.2 V

and the maximum SCLK frequency is used. Each

• Auto Power-Down: 8 nA Typ, 300 nA Max

device automatically powers down after each conver-

sion, which allows each device to save power when

• 0 V to V

Unipolar Input Range

the throughput is reduced while using the maximum

• 6-Pin SOT-23 Package

SCLK frequency.

The converter reference is taken internally from the

supply. Hence, the analog input range for these

• Battery Powered Systems

devices is 0 V to V

• Isolated Data Acquisition

These devices are available in a 6-pin SOT-23

• Medical Instruments

package and are characterized over the industrial

• Portable Communication

–40 ° C to 85 ° C temperature range.

• Portable Data Acquisition Systems

• Automatic Test Equipment

The ADS7866/67/68 are low power, miniature,

12/10/8-bit A/D converters each with a unipolar,

single-ended input. These devices can operate from a

single 1.6 V to 3.6 V supply with a 200-KSPS

throughput for ADS7866. In addition, these devices

can maintain at least a 100-KSPS throughput with a

supply as low as 1.2 V.

Micro-Power Miniature SAR Converter Family

RESOLUTION/SPEED < 200 KSPS 1 MSPS – 1.25 MSPS

12-Bit ADS7866 (1.2 V

to 3.6 V

) ADS7886 (2.35 V

to 5.25 V

)

10-Bit ADS7867 (1.2 V

to 3.6 V

) ADS7887 (2.35 V

to 5.25 V

)

8-Bit ADS7868 (1.2 V

to 3.6 V

) ADS7888 (2.35 V

to 5.25 V

)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
ADS7866 ADS7867 ADS7868 SLAS465 – JUNE 2005 1.2-V, 12-/10-/8-BIT, 200-KSPS/100-KSPS, MICRO-POWER, MINIATURE ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE FEATURES • • • • • • • • • • • Single 1.2-V to 3.6-V Supply Operation High Throughput – 200/240/280KSPS for 12/10/8-Bit VDD ≥ 1.6 V – 100/120/140KSPS for 12/10/8-Bit VDD ≥ 1.2 V ±1.
PAGE 2
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES RESOLULTION (BIT) PACKAGE TYPE PACKAGE MARKING (SYMBOL) PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE ADS7866I ±1.
PAGE 3
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 SPECIFICATIONS, ADS7866 At –40°C to 85°C, fSAMPLE = 200 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 100 KSPS and fSCLK = 1.7 MHz if 1.2 V ≤ VDD < 1.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Resolution 12 No missing codes Integral linearity Differential linearity Offset error (2) Gain error (3) Total unadjusted error (4) Bits 12 Bits –1.5 1.5 LSB (1) LSB –1 1.5 1.
PAGE 4
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 SPECIFICATIONS, ADS7866 (continued) At –40°C to 85°C, fSAMPLE = 200 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 100 KSPS and fSCLK = 1.7 MHz if 1.2 V ≤ VDD < 1.6 V (unless otherwise noted) PARAMETER VIL Input logic low level ISCLK SCLK pin leakage current ICS CS pin leakage current CIN Digital input pin capacitance TEST CONDITIONS MIN TYP MAX 1.2 V ≤ VDD < 1.6 V –0.2 0.2×VDD 1.6 V ≤ VDD < 1.8 V –0.2 0.2×VDD 1.
PAGE 5
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 SPECIFICATIONS, ADS7867 At –40°C to 85°C, fSAMPLE = 240 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 120 KSPS and fSCLK = 1.7 MHz if 1.2 V ≤ VDD < 1.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Resolution 10 No missing codes Integral linearity Gain error (3) Total unadjusted error (4) Bits –0.5 Differential linearity Offset error (2) Bits 10 0.5 LSB (1) LSB –0.5 0.5 1.
PAGE 6
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 SPECIFICATIONS, ADS7867 (continued) At –40°C to 85°C, fSAMPLE = 240 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 120 KSPS and fSCLK = 1.7 MHz if 1.2 V ≤ VDD < 1.6 V (unless otherwise noted) PARAMETER VIL Input logic low level ISCLK SCLK pin leakage current ICS CS pin leakage current CIN Digital input pin capacitance TEST CONDITIONS MIN TYP MAX 1.2 V ≤ VDD < 1.6 V –0.2 0.2×VDD 1.6 V ≤ VDD < 1.8 V –0.2 0.2×VDD 1.
PAGE 7
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 SPECIFICATIONS, ADS7868 At –40°C to 85°C, fSAMPLE = 280 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 140 KSPS and fSCLK = 1.7 MHz if 1.2 V ≤ VDD < 1.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Resolution 8 No missing codes Integral linearity Differential linearity Offset error (2) Gain error (3) Total unadjusted error (4) Bits 8 Bits –0.5 0.5 LSB (1) LSB –0.5 0.5 1.
PAGE 8
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 SPECIFICATIONS, ADS7868 (continued) At –40°C to 85°C, fSAMPLE = 280 KSPS and fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSAMPLE = 140 KSPS and fSCLK = 1.7 MHz if 1.2 V ≤ VDD < 1.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1.2 V ≤ VDD < 1.6 V –0.2 0.2×VDD 1.6 V ≤ VDD < 1.8 V –0.2 0.2×VDD 1.8 V ≤ VDD < 2.5 V –0.2 0.3×VDD 2.5 V ≤ VDD ≤ 3.6 V –0.
PAGE 9
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 TIMING REQUIREMENTS (1) (2) At –40°C to 85°C, fSCLK = 3.4 MHz if 1.6 V ≤ VDD ≤ 3.6 V; fSCLK = 1.7 MHz if 1.2 V ≤ VDD < 1.6 V, 50-pF Load on SDO Pin, unless otherwise noted PARAMETER tsample TEST CONDITIONS MIN tconvert TYP Conversion time ADS7866 13 × tC(SCLK) ADS7867 11 × tC(SCLK) UNIT Cycle time µs µs 9 × tC(SCLK) ADS7868 tC(SCLK) MAX tSU(CSF-FSCLKF) + 2 × tC(SCLK) Sample time 1.2 V ≤ VDD < 1.6 V See (3) 100 1.
PAGE 10
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 PIN CONFIGURATION ADS7866/67/68 DBV PACKAGE (TOP VIEW) REF/VDD 1 6 CS GND 2 5 SDO VIN 3 4 SCLK TERMINAL FUNCTIONS TERMINAL NAME DESCRIPTION NO. REF/VDD 1 External reference input and power supply GND 2 Ground for signal and power supply. All analog and digital signals are referred with respect to this pin. VIN 3 Analog signal input SCLK 4 Serial clock input.
PAGE 11
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7866 Normalized Amplitude − dB FFT (8192 Points) 0 −10 VDD = 1.6 V, fSAMPLE = 200 kSPS, fi = 30 kHz, SNR = 72.31 dB, SINAD = 71.97 dB, THD (9) = −83.18 dB, SFDR = 86.83 dB −20 −30 −40 −50 −60 −70 −80 −90 −100 0 10 20 30 40 50 60 70 80 90 100 45 50 fi − Input Frquency − kHz Figure 2. Normalized Amplitude − dB FFT (8192 Points) 0 −10 VDD = 1.2 V, fSAMPLE = 100 kSPS, fi = 30 kHz, SNR = 71.42 dB, SINAD = 67.
PAGE 12
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7866 (continued) SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY 300 VDD = 2.5V, 200 KSPS 78 76 74 VDD = 1.6 V, 200 KSPS 72 70 68 VDD = 1.2 V, 100 KSPS 66 VDD = 1.8 V 250 200 175 150 62 1 100 1.6 1000 VDD = 1.6 V 225 125 100 fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz TA = 85 C 375 TA = 25 C 350 TA = −40 C 325 300 275 250 225 1.8 2 fi − Input Frequency − kHz 2.2 2.4 2.6 2.8 SCLK Frequency − MHz Figure 7.
PAGE 13
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7866 (continued) DNL 1 VDD = 1.6 V, TA = 25°C, fSAMPLE = 200 KSPS, fSCLK = 3.4 MHz 0.8 DNL − LSBs 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 0 512 1024 1536 2048 2560 Code (Straight Binary in Decimal) Figure 13. 3072 3584 4096 3072 3584 4096 3072 3584 4096 INL INL − LSBs 1 VDD = 1.2 V, TA = 25°C, fSAMPLE = 100 KSPS, fSCLK = 1.7 MHz 0.8 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.
PAGE 14
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7866 (continued) MAX SUPPLY CURRENT vs SUPPLY VOLTAGE fSCLK = 3.4 MHz 375 350 450 12-Bit NMC, TA = 25°C, tSAMPLE = 2.375/fSCLK, tDIS(EOC-SDOZ)+tSU(LSBZ-CSF) = 0.375/fSCLK, 275 Throughput Rate = 16 SCLK Cycles fSCLK = 2.4 MHz 325 fSCLK = 1.
PAGE 15
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7867 Normalized Amplitude − dB FFT (8192 Points) 0 −10 −20 −30 −40 −50 VDD = 1.2 V, fSAMPLE = 100 KSPS, fi = 30 kHz, SNR = 60.419 dB, SINAD = 59.877 dB, THD (9) = −69.181 dB, SFDR = 73.682 dB −60 −70 −80 −90 −100 0 5 10 15 20 25 30 35 40 45 50 70 80 90 100 fi − Input Frequency − kHz Figure 19. VDD = 1.6 V, fSAMPLE = 200 KSPS, fi = 30 kHz, SNR = 61.173 dB, SINAD = 61.128 dB, THD (9) = −80.
PAGE 16
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7868 FFT (8192 Points) Normalized Amplitude − dB 0 VDD = 1.2 V, fSAMPLE = 100 KSPS, fi = 30 kHz, SNR = 48.669 dB, SINAD = 48.605 dB, THD (9) = −66.910 dB, SFDR = 67.041 dB −10 −20 −30 −40 −50 −60 −70 −80 −90 0 5 10 15 20 25 30 35 40 45 50 70 80 90 100 fi − Input Frequency − kHz Figure 23. FFT (8192 Points) Normalized Amplitude − dB 0 −10 −20 −30 −40 −50 VDD = 1.
PAGE 17
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 THEORY OF OPERATION The ADS7866/67/68 is a family of low supply voltage, low power, high-speed successive approximation register (SAR) analog-to-digital converters (ADCs). The devices can be operated from a supply range from 1.2 V to 3.6 V. There is no need for an external reference. The reference is derived internally from the supply voltage, so the analog input range can be from 0 V to VDD.
PAGE 18
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 THEORY OF OPERATION (continued) Table 1. Acquisition, Conversion, SCLK, and Potential Throughput Calculation PARAMETER MIN tSU(CSF-FSCLKF) MAX tDIS(EOC-SDOZ) MIN tSU(LSBZ-CSF) MAX fSCLK MIN tsample MIN tconvert MIN tCYCLE fsample SUPPLY VOLTAGE Setup time Disable time Setup time Frequency Sample time Conversion time Cycle time Theoretical sample frequency ADS7866 ADS7867 ADS7868 UNIT 1.2 V ≤ VDD < 1.6 V 192 192 192 1.
PAGE 19
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 ANALOG INPUT Figure 28 shows the analog input equivalent circuit for the ADS7866/67/68. The analog input is provided between the VIN and GND pins. When a conversion is initiated, the input signal is sampled on the internal capacitor array. When the converter enters hold mode, the input signal is captured on the internal capacitor array. The VIN input range is limited to 0 V to VDD because the reference is derived from the supply.
PAGE 20
ADS7866 ADS7867 ADS7868 www.ti.com SLAS465 – JUNE 2005 The serial output SDO is activated on the falling edge of CS. The first leading zero is available on SDO until the first falling edge of SCLK after CS falls. The remaining 3 leading zeros are shifted out on SDO on the first, second, and third falling edges of SCLK after CS falls. The MSB of the converted result follows 4 leading zeros and is clocked out on the fourth falling edge of SCLK.
PAGE 21
www.ti.com ADS7866 ADS7867 ADS7868 SLAS465 – JUNE 2005 Power-On Initialization There is no specific initialization requirement for these converters after power-on, but the first conversion might not yield a valid result. In order to set the converter in a known state, CS should be toggled low then high after VDD has stabilized during power-on. By doing this, the converter is placed in auto power-down mode, and the serial data output (SDO) is 3-stated.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 23
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 24
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) ADS7866IDBVR SOT-23 DBV 6 3000 180.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.1 1.39 4.0 8.0 Q3 ADS7866IDBVT SOT-23 DBV 6 250 180.0 8.4 3.2 3.1 1.39 4.0 8.0 Q3 ADS7867IDBVR SOT-23 DBV 6 3000 180.0 8.4 3.2 3.1 1.39 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7866IDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0 ADS7866IDBVT SOT-23 DBV 6 250 210.0 185.0 35.0 ADS7867IDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0 ADS7867IDBVT SOT-23 DBV 6 250 210.0 185.0 35.0 ADS7868IDBVR SOT-23 DBV 6 3000 210.0 185.0 35.0 ADS7868IDBVT SOT-23 DBV 6 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.