SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 FEATURES DESCRIPTION D PGA Gains: 1, 2, 4, 5, 8, 10, 16, 20 V/V D Programmable Input (Up to 4-Channel D D D D D D D D D Differential/Up to 8-Channel Single-Ended or Some Combination) 1.15-V, 2.048-V, or 2.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE ADS7871 SSOP-28 Surface Mount DB −40°C to +85°C PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS7871 ADS7871IDB Rails, 48 ADS7871 ADS7871IDBR Tape and Reel, 1000 (1) For the most current package and ordering information, see the package option addendum located at the end of this data sheet.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS For the Total System (1), −40°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input Input voltage (LNx inputs) Input capacitance (2) Input impedance (2) Linear operation −0.2 VDD + 0.2 9.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS For the Total System (1), −40°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Outputs Data coding Binary 2s complement Low-level output voltage, VOL ISINK = 5 mA ISINK = 16 mA High-level output voltage, VOH ISOURCE = 0.5 mA ISOURCE = 5 mA Logic levels Leakage current 0.4 V 0.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS For Internal Functions (1), −40°C ≤ TA ≤ 85°C, VDD = 5 V, BUFIN = 2.5 V (using external reference), 2.5-MHz CCLK and 2.5-MHz SCLK (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Multiplexer On resistance 100 Off resistance Off channel leakage current On channel leakage current Ω 1 GΩ 100 pA On channel = 0 V, Off channel = 5.2 V 100 pA On channel = 5.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 PIN ASSIGNMENTS SSOP-28 PACKAGE (TOP VIEW) LN0 LN1 LN2 LN3 LN4 LN5 LN6 LN7 RESET RISE/FALL I/O0 I/O1 I/O2 I/O3 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 BUFOUT/REFIN BUFIN VREF GND VDD CS DOUT DIN SCLK CCLK OSC ENABLE BUSY CONVERT GND Terminal Functions TERMINAL NO.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OFFSET ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE 16 12 16 VDD = 5 V, CCLK = 2.5 MHz, REFIN = 2.5 V (ext) 12 8 4 Offset Error − LSB Gain Error − LSB 8 VDD = 5 V, CCLK = 2.5 MHz, REFIN = 2.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 OUTPUT OFFSET ERROR vs COMMON-MODE VOLTAGE OUTPUT OFFSET ERROR vs POWER SUPPLY VOLTAGE 24 8 Output Offset Error − LSB 16 Gain = 20 8 Gain = 8 0 Gain = 1 −8 −16 −24 Gain = 20, TA = 25°C, CCLK = 2.5 MHz 6 Output Offset Error − LSB VDD = 5 V, TA = 25°C, CCLK = 2.5 MHz 4 2 VREF = 2.048 V 0 −2 −4 −6 −8 0 1 2 3 Common-Mode Voltage − V 4 5 2.5 3 Figure 5 3.5 4 4.5 Power Supply Voltage − V 5 5.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 TYPICAL INPUT RANGE PGA OUTPUT 6 6 VDD = 5 V, TA = 25°C VI x GAIN
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 INL − Integral Nonlinearity − LSB INL 3 1 µF Cap on, BUFOUT/REFIN, VDD = 5 V, REFIN = 2.5 V, CCLK = 2.5 MHz, TA = 25°C 2 1 0 −1 −2 −3 0 2048 4096 6144 8192 10240 12288 14336 16384 10240 12288 14336 16384 Code DNL − Differential Nonlinearity − LSB Figure 13 DNL 4 VDD = 5 V, CCLK = 2.5 MHz, VREF = 2.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 OVERVIEW The ADS7871 is a complete data acquisition device composed of an input analog multiplexer (MUX), a programmable gain amplifier (PGA) and an analog-to-digital converter (A/D). Four lines of digital input/output (I/O) are also provided. Additional circuitry provides support functions including conversion clock, voltage reference, and serial interface for control and data retrieval.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 FUNCTIONAL DESCRIPTION Multiplexer The ADS7871 has eight analog signal input pins, LN0 through LN7. These pins are connected to a network of analog switches (the MUX block in the block diagram). The switches are controlled by four bits in the Gain/Mux register. LN0 through LN7 can be configured as 8 single-ended inputs or 4 differential inputs or some other combination. Some MUX combination examples are shown in Figure 23.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Pin 26 VREF Pin 28 BUFOUT/REFIN Pin 27 BUFIN Internal Oscillator (2.5 MHz) REF BUF Enabled by Reg.7 D2, BUFE Enabled by Reg.7 D4, OSCE or Reg.7D5, OSCR or Pin 18, OSC Enable To ADC OSC CLK Reg.7 D5 OSCR = 1 Internal Reference Enabled by Pin 18 OSC Enable Reg.7 D4, OSCE 1/4 Enabled by Reg.7D3, REFE Reg.7 D5 OSCR = 0 DCLK Pin 18 OSC ENABLE 1/N Divider Pin 19 CCLK N Set by Reg.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 A/D Converter The 14-bit A/D converter in the ADS7871 is a successive approximation type. The output of the converter is 2s complement format and can be read through the serial interface MSB first or LSB first. A plot of output codes vs input voltage is shown in Figure 16.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Conversion Cycle A conversion cycle requires 50 DCLKs, where DCLK = CCLK/DF, the divided-down clock. Operation of the PGA requires 36 DCLKs: capture the input signal, auto-zero the PGA, level-shift and amplify the input signal. The period of this cycle makes certain the settling time is sufficient for gain = 20 and (source impedance of 2 kΩ or less) even if the gain is less than 20. The SAR converter takes the last 14 DCLKs.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Operating Modes The ADS7871 serial interface operates based on an instruction byte followed by an action commanded by the contents of that instruction. The 8-bit instruction word is clocked into the DIN input. There are two types of instruction bytes that may be written to the ADS7871 as determined by bit D7 of the instruction word (see Figure 17). These two instructions represent two different operating modes.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Note that the seven lower bits of this byte are written to register 4, the Gain/Mux register. All other controllable ADS7871 parameters are values previously stored in their respective registers. These values are either the power-up default values (0) or values that were previously written to one of the control registers in a register mode operation. No additional data is required for a direct mode instruction.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Register 2, the PGA Valid register, contains information that describes the nature of the problem in the event that the allowable input voltage to the PGA has been exceeded.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Write Operation To perform a write operation an instruction byte must first be written to the ADS7871 as described previously (see Figure 17). This instruction determines the target register as well as the word length (8 bits or 16 bits). The CS pin must be asserted (0) prior to the first active SCLK edge (rising or falling depending on the state of the RISE/FALL pin) that latches the first bit of the instruction byte.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Read Operation A read operation is similar to a write operation except that data flow (after the instruction byte) is from the ADS7871 to the host controller. After the instruction byte has been latched (on the eighth active edge of SCLK), the DOUT pin (and the DIN pin if in two-wire mode) begins driving data on the next nonactive edge of SCLK. This allows the host controller to have valid data on the next active edge of SCLK.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Multiplexer Addressing The last four bits in the instruction byte (during a start conversion instruction) or the Gain/Mux register (ADDR = 4) assign the multiplexer configuration for the requested conversion. The input channels may be placed in either differential or single-ended configurations. For differential configurations, the polarity of the input signal is reversible by the state of M2 (Bit D2).
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 INTERNAL USER-ACCESSIBLE REGISTERS The registers in the ADS7871 are eight bits wide. Most of the registers are reserved, the ten user-accessible registers are summarized in the register address map (see Figure 18). Detailed information for each register follows. The default power-on/reset state of all bits in the registers is 0.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 PGA Valid Register The PGA Valid register (ADDR = 2) is a read only register that contains the individual results of each of the six comparators for the PGA, VLD5 through VLD0, as shown in Figure 26. PGA VALID REGISTER ADDR D7 (MSB) D6 D5 D4 D3 D2 D1 D0 2 0 0 VLD5 VLD4 VLD3 VLD2 VLD1 VLD0 ADDR = 2 BIT SYMBOL NAME VALUE D7−D6 — — 0 These bits are not used and are always 0.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 A/D Control Register The A/D Control register (ADDR = 3) configures the CCLK divider and read back mode option as shown in Figure 27. ADC CONTROL REGISTER ADDR D7 (MSB) D6 D5 D4 D3 D2 D1 D0 3 0 0 BIN 0 RBM1 RBM0 CFD1 CFD0 ADDR = 3 BIT SYMBOL NAME VALUE D7−D6 — — 0 These bits are reserved and must always be written 0.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Gain/Mux Register The Gain/Mux register (ADDR = 4) contains the bits that configure the PGA gain (G2 − G0) and the input channel selection (M3 − M0) as shown in Figure 28. This register is also updated when direct mode is used to start a conversion so its bit definition is compatible with the instruction byte.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Digital Input/Output State Register The Digital I/O State register (ADDR = 5) contains the state of each of the four digital I/O pins. Each pin can function as a digital input (the state of the pin is set by an external signal connected to it) or a digital output (the state of the pin is set by data from a serial input to the ADS7871).
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Digital I/O Control Register The Digital I/O Control register (ADDR = 6) contains the information that determines whether each of the four digital I/O lines is configured as an input or output. Setting the appropriate OE bit to 1 enables the corresponding I/O pin as an output. Setting the appropriate OE bit to 0 enables the corresponding I/O pin as an input (see Figure 30).
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Reference/Oscillator Configuration Register The Reference/Oscillator Configuration register (ADDR = 7) determines whether the internal oscillator is used (OSCE and OSCR), whether the internal voltage reference and buffer are on or off (REFE and BUFE), and whether the reference is 2.5 V, 2.048 V, or 1.15 V as shown in Figure 31.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Serial Interface Control Register The Serial Interface Control register (ADDR = 24), see Figure 32, allows certain aspects of the serial interface to be controlled by the user. It controls whether data is presented MSB or LSB first and whether the serial interface is configured for 2-wire or 3-wire operation, and it determines proper timing control for 8051-type microprocessor interfaces.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Serial Interface Timing (8051 Bit) The 8051 bit changes the timing of when the DIN pin goes to high impedance at the end of an operation. When the bit is a 1, the pin goes to high impedance on the last active SCLK edge of the last byte of data transfer instead of waiting for the next inactive edge, or CS to go inactive. This allows the ADS7871 to disconnect from the data lines soon enough to avoid contention with an 80C51-type interface.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Figure 35 shows the timing for entering the high impedance state when the 8051 bit is set. Notice that on the last bit of the read operation the DIN (and DOUT) pin goes to the high impedance state on the active edge of SCLK instead of waiting for the inactive edge of SCLK or CS going high as shown in Figure 33 and Figure 34. This is for compatibility with 80C51 mode 0 type serial interfaces.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 STARTING A CONVERSION THROUGH THE SERIAL INTERFACE There are two methods of starting a conversion cycle through the serial interface. The first (nonaddressed or direct mode) is by using the start conversion byte as described earlier. The second (addressed mode) is by setting the CNV/BSY bit of register 4 or register 5 by performing a write instruction.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Figure 38 shows an example of a conversion start using an 8-bit write operation to the Gain/Mux register with the CNV/BSY bit set to 1. The double rising arrow on SCLK indicates where the data is latched into the Gain/Mux register and the double arrow on CCLK indicates when the conversion starts. The example is for LSB first, CCLK divider = 1, and SCLK active on the rising edge.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 STARTING A CONVERSION USING THE CONVERT PIN A conversion can also be started by an active (rising) edge on the CONVERT pin. Similar to the CNV/BSY register bit, the conversion starts on the second falling edge of CCLK after the CONVERT rising edge. The CONVERT pin must stay high for at least two CCLK periods. CONVERT must also be low for at least two CCLK periods before going high.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 Mode 1 In this mode, the serial interface configures itself to clockout a conversion result as soon as a conversion is started. This is useful since a read instruction is not required so eight SCLK cycles are saved. This mode operates like an implied sixteen bit read instruction byte for ADDR = 1 was sent to the ADS7871 after starting the conversion.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 In Figure 42 the result of the just requested conversion is retrieved. The microcontroller must wait for BUSY to go inactive before clocking out the ADC Output register. CS must stay low while waiting for BUSY. This example is for LS byte first, CCLK divider = 1, and SCLK active on the falling edge. Notice that the DOUT pin is not driven with correct data until the appropriate active edge of SCLK.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 APPLICATION INFORMATION REQUIRED SUPPORT ELEMENTS As with any precision analog integrated circuit, good power supply bypassing is required. A low ESR ceramic capacitor in parallel with a large value electrolytic capacitor across the supply line furnishes the required performance. Typical values are 0.1 µF and 10 µF respectively. Noise performance of the internal voltage reference circuit is improved if a ceramic capacitor of approximately 0.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 APPLICATION INFORMATION MICROCONTROLLER CONNECTIONS The ADS7871 is quite flexible in interfacing to various microcontrollers. Connections using the hardware mode of two types of controllers (Motorola M68HC11, Intel 80C51) are described below.
www.ti.com SLAS370C − APRIL 2002 − REVISED OCTOBER 2004 APPLICATION INFORMATION Intel 80C51 The Intel 80C51 operated in serial port mode 0 has a two-wire (three-wire if an additional I/O pin is used for CS) serial interface. The TXD pin provides the clock for the serial interface and RXD serves as the data input and output. The data is transferred LSB first. Best compatibility is achieved by connecting the RISE/FALL pin of the ADS7871 high (rising edge of SCLK active).
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS7871IDBR Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 8.1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.4 2.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 13-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7871IDBR SSOP DB 28 1000 367.0 367.0 38.
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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