Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply SOT 23 6

 

  

FEATURES APPLICATIONS

DESCRIPTION

ADS7887

ADS7888

SLAS468 – JUNE 2005

10-/8-Bit, 1.25-MSPS, MICRO-POWER, MINIATURE

SAR ANALOG-TO-DIGITAL CONVERTERS

• Base Band Converters in Radio Communi-

• 1.25-MHz Sample Rate Serial Device

cation

• 10-Bit Resolution – ADS7887

• Motor Current/Bus Voltage Sensors in Digital

• 8-Bit Resolution – ADS7888

Drives

• Zero Latency

• Optical Networking (DWDM, MEMS Based

• 25-MHz Serial Interface

Switching)

• Supply Range: 2.35 V to 5.25 V

• Optical Sensors

• Battery Powered Systems

• Typical Power Dissipation at 1.25 MSPS:

• Medical Instrumentations

– 3.8 mW at 3-V V

• High-Speed Data Acquisition Systems

– 8 mw at 5-V V

• High-Speed Closed-Loop Systems

• ± 0.35 LSB INL, DNL – ADS7887

• ± 0.15 LSB INL, ± 0.1 LSB DNL – ADS7888

• 61dB SINAD, -84 dB THD – ADSA7887

• 49.5 dB SINAD, -67.5 dB THD – ADS7888

• Unipolar Input Range: 0 V to V

• Power Down Current: 1 µA

• Wide Input Bandwidth: 15 MHz at 3 dB

• 6-Pin SOT23 and SC70 Packages

The ADS7887 is a 10-bit, 1.25-MSPS analog-to-digital converter (ADC), and the ADS7888 is a 8-bit, 1.25-MSPS

ADC. The devices include a capacitor based SAR A/D converter with inherent sample and hold. The serial

interface in each device is controlled by the CS and SCLK signals for glueless connections with microprocessors

and DSPs. The input signal is sampled with the falling edge of CS, and SCLK is used for conversion and serial

data output.

The devices operate from a wide supply range from 2.35 V to 5.25 V. The low power consumption of the devices

make them suitable for battery-powered applications. The devices also include a power saving powerdown

feature for when the devices are operated at lower conversion speeds.

The high level of the digital input to the device is not limited to device V

. This means the digital input can go as

high as 5.25 V when device supply is 2.35 V. This feature is useful when digital signals are coming from other

circuit with different supply levels. Also this relaxes restriction on power up sequencing.

The ADS7887 and ADS7888 are available in 6-pin SOT23 and SC70 packages and are specified for operation

from -40°C to 125°C.

Micro-Power Miniature SAR Converter Family

BIT < 300 KSPS 300 KSPS – 1.25 MSPS

12-Bit ADS7866 (1.2 V

to 3.6 V

) ADS7886 (2.35 V

to 5.25 V

)

10-Bit ADS7867 (1.2 V

to 3.6 V

) ADS7887 (2.35 V

to 5.25 V

)

8-Bit ADS7868 (1.2 V

to 3.6 V

) ADS7888 (2.35 V

to 5.25 V

)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
ADS7887 ADS7888 SLAS468 – JUNE 2005 10-/8-Bit, 1.25-MSPS, MICRO-POWER, MINIATURE SAR ANALOG-TO-DIGITAL CONVERTERS FEATURES APPLICATIONS • • • • • • • • • • • • • • • • 1.25-MHz Sample Rate Serial Device 10-Bit Resolution – ADS7887 8-Bit Resolution – ADS7888 Zero Latency 25-MHz Serial Interface Supply Range: 2.35 V to 5.25 V Typical Power Dissipation at 1.25 MSPS: – 3.8 mW at 3-V VDD – 8 mw at 5-V VDD ±0.35 LSB INL, DNL – ADS7887 ±0.15 LSB INL, ±0.
PAGE 2
ADS7887 ADS7888 www.ti.
PAGE 3
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION (1) DEVICE MAXIMUM INTEGRAL LINEARITY (LSB) ADS7887 MAXIMUM DIFFERENTIAL LINEARITY (LSB) ±0.75 ADS7888 ±0.3 NO MISSING CODES AT RESOLUTION (BIT) ±0.5 PACKAGE TYPE PACKAGE DESIGNATOR 6-Pin SOT23 DBV 10 ±0.
PAGE 4
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 ADS7887 SPECIFICATIONS +VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, fsample = 1.25 MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD V ANALOG INPUT Full-scale input voltage span (1) Absolute input voltage range Ci Input capacitance (2) IIlkg Input leakage current 0 +IN –0.20 TA = 125°C VDD+0.20 V 21 pF 40 nA 10 Bits SYSTEM PERFORMANCE Resolution No missing codes 10 Bits –0.75 ±0.35 0.75 LSB (3) Differential nonlinearity –0.
PAGE 5
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 ADS7887 SPECIFICATIONS (continued) +VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, fsample = 1.25 MHz PARAMETER Power dissipation in static state TYP MAX VDD = 5 V TEST CONDITIONS MIN 5.5 7.5 VDD = 3 V 3 4.5 UNIT mW Power down time 0.1 µs Power up time 0.
PAGE 6
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 ADS7888 SPECIFICATIONS +VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, fsample = 1.25 MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD V ANALOG INPUT Full-scale input voltage span (1) Absolute input voltage range Ci Input capacitance (2) IIlkg Input leakage current 0 +IN –0.20 TA = 125°C VDD+0.20 V 21 pF 40 nA 8 Bits SYSTEM PERFORMANCE Resolution No missing codes 8 Bits ±0.15 0.3 LSB (3) –0.3 ±0.1 0.3 LSB –0.5 ±0.15 0.
PAGE 7
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 ADS7888 SPECIFICATIONS (continued) +VDD = 2.35 V to 5.25 V, TA = –40°C to 125°C, fsample = 1.25 MHz PARAMETER TEST CONDITIONS Power dissipation in static state TYP MAX VDD = 5 V MIN 5.5 7.5 VDD = 3 V 3 4.5 UNIT mW Power down time 0.1 µs Power up time 0.
PAGE 8
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 DEVICE INFORMATION SOT23/SC70 PACKAGE (TOP VIEW) VDD 1 6 CS GND 2 5 SDO VIN 3 4 SCLK TERMINAL FUNCTIONS TERMINAL NAME I/O NO. DESCRIPTION VDD 1 – Power supply input also acts like a reference voltage to ADC. GND 2 – Ground for power supply, all analog and digital signals are referred with respect to this pin.
PAGE 9
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 ADS7888 NORMAL OPERATION The cycle begins with the falling edge of CS . This point is indicated as a in Figure 2. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 4 leading zeros, followed by 8-bit data in MSB first format and padded by 4 lagging zeros.
PAGE 10
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 td6 td5 CS 1 2 3 4 5 9 10 16 SCLK SDO Figure 4. Entering Power Down Mode A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power down mode. For the device to come to the fully powered up condition it takes 0.8 µs. CS can be pulled high any time after the 10th falling edge as shown in Figure 5. It is not necessary to continue until the 16th clock if the next conversion starts 0.
PAGE 11
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7887, ADS7888 SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SCLK FREQUENCY 1.80 1.8 1.60 125 C 1.4 −40 C 1.3 1.2 1.40 1.20 2.35 V VDD 1 0.80 0.60 1 0.8 0.6 0.4 0.40 1.1 1 2.35 I DD − Supply Current − mA I DD − Supply Current − mA 25 C VDD = 5 V, fSCLK = 25 MHz, TA = 25 C, Power Down SCLK = Free Running 1.2 5 V VDD 1.6 1.5 1.4 TA = 25 C fs = 1.25 MSPS, fSCLK = 25 MHz 0.2 0.20 3.075 3.8 4.
PAGE 12
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7887 SIGNAL-TO-NOISE AND DISTORTION vs SUPPLY VOLTAGE 62 61.7 61.5 61.3 61.1 60.9 60.7 60.5 1 10 100 fi − Input Frequency − kHz 61.7 61.6 61.5 61.4 61.3 61.2 −82 −83 −84 −85 −86 −87 −88 −89 61.1 3.075 3.8 4.525 −90 5.25 1 10 fi − Input Frequency − kHz 100 Figure 11. Figure 12.
PAGE 13
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7887 (continued) GAIN ERROR vs FREE-AIR TEMPERATURE 1 0.8 fs = 1.25 MSPS, VDD = 5 V E G − Gain Error − LSBs 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 −1 −40 −20 0 20 40 60 80 100 120 TA − Free-Air Temperature − °C Figure 19. DNL − LSBs DNL 0.5 0.4 0.3 0.2 0.1 VDD = 2.35 V, fs = 1.25 MSPS, TA = 25 C 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 256 512 768 1024 768 1024 Output Code Figure 20. INL − LSBs INL 0.5 0.4 0.3 0.2 0.
PAGE 14
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7887 (continued) FFT 0 VDD = 2.35 V, fs = 1.25 MSPS, TA = 25 C fi = 100 kHz, 8192 Points Amplitude − dB −20 −40 −60 −80 −100 −120 −140 0 125000 250000 375000 fi − Input Frequency − kHz Figure 22.
PAGE 15
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7888 SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY SIGNAL-TO-NOISE AND DISTORTION vs SUPPLY VOLTAGE 49.8 49.7 49.6 49.5 49.4 49.3 49.2 49.1 1 10 100 fi − Input Frequency − kHz fs = 1.25 MSPS, fi = 100 kHz, TA = 25 C 49.9 49.8 49.7 49.6 49.5 49.4 49.3 49.2 49.1 VDD = 5 V, fs = 1.25 MSPS, TA = 25 C −65.5 −66 −66.5 −67 −67.5 −68 −68.5 −69 −69.5 49 2.35 1000 THD − Total Harmonic Distortion − dB 49.
PAGE 16
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7888 (continued) GAIN ERROR vs FREE-AIR TEMPERATURE 0.3 fs = 1.25 MSPS, TA = 25 C E G − Gain Error − LSBs 0.2 0.1 0 −0.1 −0.2 −0.3 −40 −7 26 59 92 125 TA − Free-Air Temperature − °C Figure 32. DNL 0.5 DNL − LSBs 0.4 0.3 VDD = 2.35 V, fs = 1.25 MSPS, TA = 25 C 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0 64 128 192 256 192 256 Output Code Figure 33. INL − LSBs INL 0.5 0.4 0.3 0.2 0.1 VDD = 2.35 V, fs = 1.
PAGE 17
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 TYPICAL CHARACTERISTICS ADS7888 (continued) FFT 0 TA = 25 C fi = 100 kHz, 8192 Points Amplitude − dB −20 −40 −60 −80 −100 −120 0 125000 250000 375000 500000 625000 fi − Input Frequency − kHz Figure 35.
PAGE 18
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 APPLICATION INFORMATION VDD 20 60 IN 16 pF 60 5 pF GND Figure 36. Typical Equivalent Sampling Circuit Driving the VIN and VDD Pins of the ADS7887 and ADS7888 The VIN input to the ADS7887 and ADS7888 should be driven with a low impedance source. In most cases additional buffers are not required. In cases where the source impedance exceeds 200 Ω, using a buffer would help achieve the rated performance of the converter.
PAGE 19
ADS7887 ADS7888 www.ti.com SLAS468 – JUNE 2005 APPLICATION INFORMATION (continued) 5V C1 R1 10 7V _ R2 VDD CS VIN SDO GND SCLK + 1 F 1 F 10 nF Figure 39.
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ ADS7887SDBVR SOT-23 3000 177.8 9.7 3.2 DBV 6 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.1 1.39 4.0 8.0 Q3 ADS7887SDBVT SOT-23 DBV 6 250 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3 ADS7887SDCKR SC70 DCK 6 3000 177.8 9.7 2.3 2.52 1.2 4.0 8.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7887SDBVR SOT-23 DBV 6 3000 184.0 184.0 50.0 ADS7887SDBVT SOT-23 DBV 6 250 184.0 184.0 50.0 ADS7887SDCKR SC70 DCK 6 3000 184.0 184.0 50.0 ADS7887SDCKT SC70 DCK 6 250 184.0 184.0 50.0 ADS7888SDBVR SOT-23 DBV 6 3000 184.0 184.0 50.0 ADS7888SDBVT SOT-23 DBV 6 250 184.0 184.0 50.
PAGE 24
PAGE 25
PAGE 26
PAGE 27
PAGE 28
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.