Datasheet

PL_PDRST

PDRST/

ADS8028

SBAS549B –MAY 2011–REVISED MARCH 2012

www.ti.com

RESET

The ADS8028 can be RESET by pulling the PD/RST pin to a logic low state for no longer than 60 ns. This input

is asynchronous to the clock. On RESET, the Control Register bits are set to the default state and the

temperature sensor averaging feature is reset and disabled. When the PD/RST is pulled back to a logic high

state, the ADS8028 is placed in normal mode. One valid write operation must be executed on the Control

Note that PD/RST is a dual-function pin. Figure 39 shows the timing of this pin and Table 4 explains the usage of

this pin.

Figure 39. PD/RST Pin Timing

Table 4. PD/RST Pin Functionality

CONDITION DEVICE MODE

PL_PDRST

< 60 ns RESET (device does not enter power-down mode)

Device RESET. The ADS8028 may or may not enter power-down

60 ns < t

PL_PDRST

< 90 ns mode.

This setting is not recommended.

PL_PORST

> 90 ns Device enters power-down mode

POWER SUPPLY

The ADS8028 has two separate power supplies: AVDD and DVDD. The ADC operates on an AVDD power

supply; the DVDD supply is used for the interface circuits. AVDD and DVDD can be set independently to any

value within the permissible range; however, care must be taken to ensure that Equation 7 is fulfilled.

DVDD ≤ AVDD + 0.3 V (7)

The ADS8028 contains an internal power-on-reset (POR) circuit that resets the Control Register to the default

value (all zeros). Therefore, by default, the ADS8028 powers up in internal reference mode. To continue with the

internal reference, a 5.5-ms delay must elapse before initiating the first conversion.

To operate with an external reference, there is no required delay for the internal reference to power-up. The

ADS8028 digital interface is fully functional 500 µs after power-up. Therefore, after a 500-µs delay, a valid write

operation can be executed to the Control Register to program the device in external reference mode and to

select the channels for conversion.

Product Folder Link(s): ADS8028