Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SSOP 28

12-Bit, 20MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● HIGH SFDR: 74dB at 9.8MHz f

● HIGH SNR: 68dB

● LOW POWER: 300mW

● LOW DLE: 0.25LSB

● FLEXIBLE INPUT RANGE

● OVER-RANGE INDICATOR

APPLICATIONS

● STUDIO CAMERAS

● IF AND BASEBAND DIGITIZATION

● COPIERS

● TEST INSTRUMENTATION

DESCRIPTION

The ADS805 is a 20MHz, high dynamic range, 12-bit, pipelined

Analog-to-Digital Converter ADC. This converter includes a

high-bandwidth track-and-hold that gives excellent spurious

performance up to and beyond the Nyquist rate. This high-

bandwidth, linear track-and-hold minimizes harmonics and

has low jitter, leading to excellent Signal-to-Noise Ratio

(SNR) performance. The ADS805 is also pin-compatible with

the 10MHz ADS804 and the 5MHz ADS803.

The ADS805 provides an internal reference or an external

reference can be used. The ADS805 can be programmed for

a 2Vp-p input range which is the easiest to drive with a single

op amp and provides the best spurious performance. Alter-

natively, the 5Vp-p input range can be used for the lowest

input-referred noise of 0.09LSBs rms giving superior imaging

performance. There is also the capability to set the input

range between 2Vp-p and 5Vp-p, either single-ended or

differential. The ADS805 also provides an over-range flag

that indicates when the input signal has exceeded the

converter’s full-scale range. This flag can also be used to

reduce the gain of the front end signal conditioning circuitry.

The ADS805 employs digital error techniques to provide

excellent differential linearity for demanding imaging applica-

tions. Its low distortion and high SNR give the extra margin

needed for communications, medical imaging, video, and

test instrumentation applications. The ADS805 is available in

an SSOP-28 package.

12-Bit

Pipelined

ADC Core

Reference and

Mode Select

Reference Ladder

and Driver

Timing Circuitry

Error

Correction

Logic

3-State

Outputs

T&H

D11

•

CLK

ADS805

VDRV

SEL REFBV

REF

REFT

INV

OVR

ADS805

SBAS073B – JANUARY 1997 – REVISED NOVEMBER 2002

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (19 pages)

PAGE 1
ADS805 ADS 805 E SBAS073B – JANUARY 1997 – REVISED NOVEMBER 2002 12-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS ● ● ● ● ● ● ● ● ● ● HIGH SFDR: 74dB at 9.8MHz fIN HIGH SNR: 68dB LOW POWER: 300mW LOW DLE: 0.25LSB FLEXIBLE INPUT RANGE OVER-RANGE INDICATOR DESCRIPTION STUDIO CAMERAS IF AND BASEBAND DIGITIZATION COPIERS TEST INSTRUMENTATION natively, the 5Vp-p input range can be used for the lowest input-referred noise of 0.09LSBs rms giving superior imaging performance.
PAGE 2
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY +VS ....................................................................................................... +6V Analog Input ............................................................. –0.3V to (+VS) + 0.3V Logic Input ............................................................... –0.3V to (+VS) + 0.3V This integrated circuit can be damaged by ESD.
PAGE 3
ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, and single-ended input and sampling rate = 20MHz, unless otherwise specified.
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PIN CONFIGURATION PIN DESCRIPTIONS Top View SSOP OVR 1 28 VDRV B1 2 27 +VS B2 3 26 GND B3 4 25 IN B4 5 24 GND B5 6 23 IN B6 7 22 REFT B7 8 21 CM B8 9 20 REFB B9 10 19 VREF B10 11 18 SEL B11 12 17 GND B12 13 16 +VS CLK 14 15 OE ADS805 PIN DESIGNATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OVR B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 CLK OE 16 17 18 19 20 21 22 23 24 25 26 27 28 +VS GND SEL VREF REFB CM REFT IN GND IN GND +VS VDRV DESCRIPTION Over-Range
PAGE 5
TYPICAL CHARACTERISITCS At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 20MHz, unless otherwise specified. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 9.8MHz –20 –40 –40 Amplitude (dB) Amplitude (dB) fIN = 500kHz –20 –60 –80 –100 –60 –80 –100 –120 –120 0 2.0 4.0 6.0 8.0 10.0 0 2.0 4.0 Frequency (MHz) 2-TONE INTERMODULATION DISTORTION 8.0 10.0 DIFFERENTIAL LINEARITY ERROR 0 1.0 fIN = 9.
PAGE 6
TYPICAL CHARACTERISITCS (Cont.) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 20MHz, unless otherwise specified. DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE DYNAMIC PERFORMANCE vs INPUT FREQUENCY 85 0.6 SFDR fIN = 9.8MHz 0.4 DLE (LSB) SFDR, SNR (dBFS) 80 75 70 0.2 fIN = 500kHz SNR 65 60 0 0.
PAGE 7
TYPICAL CHARACTERISITCS (Cont.) At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, and sampling rate = 20MHz, unless otherwise specified. OUTPUT NOISE HISTOGRAM (DC Input, VIN = 5Vp-p Range) 800k 800k 600k 600k Counts Counts OUTPUT NOISE HISTOGRAM (DC Input) 400k 200k 400k 200k 0 0 N–2 N–1 N N+1 N+2 N–2 N–1 Code N N+1 N+2 Code UNDERSAMPLING (Differential Input, 2Vp-p) 0 fS = 20MHz fIN = 41MHz SNR = 63.2dBFS SFDR = 76.
PAGE 8
APPLICATION INFORMATION configurations. This will decouple the op amp’s output from the capacitive load and avoid gain peaking, which can result in increased noise. For best spurious and distortion performance, the resistor value should be kept below 100Ω. Furthermore, the series resistor, together with the 100pF capacitor, establish a passive low-pass filter, limiting the bandwidth for the wideband noise, thus helping improve the signal-to-noise performance.
PAGE 9
RF +VS RIN +1V 0 VIN –1V R3 2kΩ RS 50Ω REFT IN OPA691 2Vp-p 22pF R1 ADS805 R2 +VS +2.5V + 0.1µF IN 0.1µF 10µF (+1V) VREF REFB R4 2kΩ SEL NOTE: RF = RIN, G = –1 FIGURE 2. DC-Coupled, Single-Ended Input Configuration with DC-level Shift. offset. The selection criteria for an appropriate op amp should include the input bias current, output voltage swing, distortion, and noise specification. Note that in this example the overall signal phase is inverted.
PAGE 10
A simple model of the internal reference circuit is shown in Figure 4. The internal blocks are a 1V-bandgap voltage reference, buffer, the resistive reference ladder and the drivers for the top and bottom reference which supply the necessary current to the internal nodes. As shown, the output of the buffer appears at the VREF pin. The full-scale input span of the ADS805 is determined by the voltage at VREF, according to Equation 1: Full-Scale Input Span = 2 • VREF ADS805 VREF 10µF + 0.1µF + 0.1µF 0.
PAGE 11
SELECTING THE INPUT RANGE AND REFERENCE EXTERNAL REFERENCE OPERATION Figures 7 through 9 show a selection of circuits for the most common input ranges when using the internal reference of the ADS805. All examples are for single-ended input and operate with a nominal common-mode voltage of +2.5V. Depending on the application requirements, it might be advantageous to operate the ADS805 with an external reference.
PAGE 12
MSB Over = H OVR Under = H FIGURE 11. External Logic for Decoding Under-Range and Over-Range Conditions. CLOCK INPUT REQUIREMENTS Clock jitter is critical to the SNR performance of high-speed, high-resolution ADCs. It leads to aperture jitter (tA) which adds noise to the signal being converted. The ADS805 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by Equation 2.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.com 23-May-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS805E/1K Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 8.1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.4 2.5 12.0 16.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 31-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS805E/1K SSOP DB 28 1000 367.0 367.0 38.
PAGE 17
PAGE 18
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 19
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