Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External VSSOP 10

CDAC

COMP

SAR

O/P

Drive

I/P

Shift

Reg

ConversionandI/O

ControlLogic

IN+

IN-

REFIN

+VA

+VBD

SDO

SDI

SCLK

CONVST

GND

ADS8318

www.ti.com

SLAS568A –MAY 2008–REVISED MARCH 2011

16-BIT, 500-KSPS, SERIAL INTERFACE MICROPOWER, MINIATURE,

SAR ANALOG-TO-DIGITAL CONVERTER

Check for Samples: ADS8318

FEATURES

DESCRIPTION

The ADS8318 is a 16-bit, 500-KSPS analog-to-digital

• 500-kHz Sample Rate

converter. It operates with a 2.048-V to 5.5-V external

• 16-Bit Resolution

reference. The device includes a capacitor based,

• Zero Latency at Full Speed

SAR A/D converter with inherent sample and hold.

• Unipolar, Differential Input, Range: –V

ref

to V

ref

The devices includes a 50-MHz SPI compatible serial

• SPI Compatible Serial Interface with Daisy

interface. The interface is designed to support daisy

chaining or cascading of multiple devices. Also a

Chain Option

Busy Indicator makes it easy to synchronize with the

• Excellent Performance:

digital host.

– 95.2dB SNR Typ at 10-kHz I/P

The ADS8318 unipolar differential input range

– –108dB THD Typ at 10-kHz I/P

supports a differential input swing of –V

ref

to +V

ref

with

– ±1.0 LSB Max INL

a common-mode of +V

ref

/2.

– ±0.75 LSB Max DNL

Device operation is optimized for very low power

• Low Power Dissipation: 18 mW Typ at 500

operation, and the power consumption directly scales

KSPS

with speed. This feature makes it attractive for lower

speed applications.

• Power Scales Linearly with Speed: 3.6 mW/100

KSPS

It is available in 10-pin MSOP and SON packages.

• Power Dissipation During Power-Down State:

0.25 μW Typ

• 10-Pin MSOP and SON Packages

APPLICATIONS

• Battery Powered Equipments

• Data Acquisition Systems

• Instrumentation and Process Control

• Medical Electronics

• Optical Networking

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com 16-BIT, 500-KSPS, SERIAL INTERFACE MICROPOWER, MINIATURE, SAR ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS8318 FEATURES DESCRIPTION • • • • • The ADS8318 is a 16-bit, 500-KSPS analog-to-digital converter. It operates with a 2.048-V to 5.5-V external reference. The device includes a capacitor based, SAR A/D converter with inherent sample and hold.
PAGE 2
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, fSAMPLE = 500 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (1) Operating input range +IN – (–IN) –Vref Vref +IN – 0.1 Vref + 0.1 –IN – 0.1 Input common-mode range 0 Input capacitance +IN and -IN terminal to GND Input leakage current During acquisition V Vref + 0.1 Vref/2 Vref/2+0.
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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 5 V to 2.375 V, Vref = 4 V, fSAMPLE = 500 kHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS –114 VIN 0.4 dB below FS at 1 kHz, Vref = 5 V THD Total harmonic distortion (5) VIN 0.4 dB below FS at 10 kHz, Vref = 5 V –108 VIN 0.4 dB below FS at 100 kHz, Vref = 5 V –91.5 VIN 0.
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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TIMING REQUIREMENTS All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD ≥ 3.
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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TIMING REQUIREMENTS All specifications typical at –40°C to 85°C, +VA = 5 V, +3.1 V > +VBD ≥ 2.
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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com PIN ASSIGNMENTS MSOP PACKAGE (TOP VIEW) REFIN +VA IN+ INGND 1 10 2 9 3 8 4 7 5 6 SON PACKAGE (TOP VIEW) +VBD SDI SCLK SDO CONVST REFIN +VA IN+ INGND 1 10 2 9 3 8 4 7 5 6 +VBD SDI SCLK SDO CONVST Terminal Functions TERMINAL NO. I/O NAME DESCRIPTION ANALOG PINS 1 REFIN I Reference (positive) input. Decouple with GND pin using 0.1-μF bypass capacitor and 10-μF storage capacitor.
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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) GAIN ERROR vs REFERENCE VOLTAGE OFFSET ERROR vs FREE-AIR TEMPERATURE -0.001 1 -0.002 0.9 -0.006 -0.007 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, TA = 30°C -0.008 -0.009 -0.01 2 0 0.7 Gain Error - %FSR Offset Error - mV -0.005 0.6 0.5 0.4 0.3 0.2 2.5 3 3.5 4 4.5 Vref - Reference Voltage - V -0.006 -0.008 0 -40 5 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C -0.
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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.8 DNLMAX 0.4 0.2 0 -0.2 ENOB - Effective Number Of Bits - LSBs 0.6 DNLMIN -0.4 -0.6 -0.8 INLMAX 0.6 0.4 +VA = 5 V +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS 0.2 0 -0.2 -0.4 INLMIN -0.6 -0.
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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SPURIOUS FREE DYNAMIC RANGE vs REFERENCE VOLTAGE SIGNAL-TO-NOISE + DISTORTION vs REFERENCE VOLTAGE 121 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 120 119 118 117 116 96 95.5 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 95 94.5 94 95.5 +VA = 5 V +VBD = 2.7 V, fs = 500 KSPS, fi = 1.9 kHz, TA = 30°C 95 94.5 94 93.5 93.5 2.5 3 3.5 4 4.
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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SINAD @ -10 dB 97 200000 95 SINAD @ -0.5 dB +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 150000 93 91 100000 +VA = 5 V +VBD = 2.
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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) DNL DNL - LSBs 1 0.8 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 10000 20000 30000 Codes 40000 50000 60000 Figure 42. INL 1 +VA = 5 V, +VBD = 2.7 V, Vref = 5 V, fs = 500 KSPS, TA = 30°C 0.8 INL - LSBs 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 10000 20000 30000 40000 Codes 50000 60000 Figure 43.
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ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com DETAILED DESCRIPTIONS AND TIMING DIAGRAMS The ADS8318 is a high-speed, low power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample/hold function. The ADS8318 is a single channel device. The analog input is provided to two input pins: +IN and -IN.
PAGE 14
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com When the conversion is over, the device enters the acquisition phase and powers down. On the falling edge of CONVST, SDO comes out of three state, and the device outputs the MSB of the data. After this, the device outputs the next lower data bits on every falling edge of SCLK. SDO goes to 3-state after the 16th falling edge of SCLK or CONVST high, whichever occurs first.
PAGE 15
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com tcyc t1 CONVST tacq tcnv ACQUISITION CONVERSION ACQUISITION tclkl t2 1 SCLK 2 3 16 t3 SDO D15 tclk D14 D1 17 tclkh tdis D0 Figure 48. Interface Timing Diagram, 3 Wire CS Mode With Busy Indicator (SDI = 1) 4 Wire CS Mode Without Busy Indicator CS1 CS2 CNV CONVST SDI CONVST SDO SCLK SDI SDO SDI SCLK CLK ADS8318#1 ADS8318#2 Digital Host Figure 49.
PAGE 16
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com brings SDO out of 3-state and the device outputs the MSB of the data. Subsequent to this the device outputs the next lower data bits on every falling edge of SCLK. SDO goes to three state after the 16th falling edge of SCLK or SDI (CS) high, whichever occurs first. As shown in Figure 49, it is possible to hook multiple devices on the same data bus.
PAGE 17
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com Care needs to be taken so that CONVST and SDI are not low together at any time during the cycle. tcyc t6 CNVST t5 SDI (CS) t 4 tacq tcnv ACQUISITION CONVERSION ACQUISITION tclkh t2 1 SCLK 2 3 t3 SDO D15 17 16 tclkl tdis tclk D14 D1 D0 Figure 52. Interface Timing Diagram, 4 Wire CS Mode With Busy Indicator Daisy Chain Mode Daisy chain mode is selected if SDI is low at the time of CONVST rising edge.
PAGE 18
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com SDI and CONVST are low together. The rising edge of CONVST while SDI is low selects daisy chain mode and the device samples the analog input and enters the conversion phase. It is necessary that SCLK is low at the rising edge of CONVST so that the device does not generate a busy indicator at the end of the conversion. In this mode CONVST continues to be high from the start of the conversion until all of the data bits are read.
PAGE 19
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com and CONVST are wired together, and the setup time of SDI to rising edge of CONVST is adjusted so that the device still enters chain mode even though SDI and CONVST rise together. It is necessary that SCLK is high at the rising edge of CONVST so that the device generates a busy indicator at the end of the conversion. In this mode, CONVST continues to be high from the start of the conversion until all of the data bits are read.
PAGE 20
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com APPLICATION INFORMATION ANALOG INPUT When the converter samples the input, the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array. The voltage on the +IN and –IN inputs individually is limited between GND –0.1 V and Vref + 0.1 V; where as the differential signal range [(+IN) – (–IN)] is 2Vref (–Vref to +Vref) with a common mode of (Vref/2).
PAGE 21
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com Figure 58. Unipolar Differential Input Drive Configuration Configuration for Bipolar Single-Ended Input The following circuit shows a way to convert a single-ended bipolar input to the unipolar differential input needed for for converter. Note that the higher values of the resistors at the input of the top OPA may reduce power consumption of the circuit but increase noise in the driving circuit.
PAGE 22
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com 50 W - REF5050 OUT TRIM + + - 47 mF, OPA365 1.5 W ESR (High ESR) + IN+ - 4.7 mF, Low ESR 10 mF REFIN ADS8318 IN- Figure 60. External Reference Driving Circuit REF5050 OUT + - 47 mF, 1.5 W ESR (High ESR) 22 mF REFIN TRIM + - 4.7 mF, Low ESR IN+ ADS8318 IN- Figure 61. Direct External Reference Driving Circuit POWER SAVING The ADS8318 has an auto power-down feature. The device powers down at the end of every conversion.
PAGE 23
ADS8318 SLAS568A – MAY 2008 – REVISED MARCH 2011 www.ti.com REVISION HISTORY Changes from Original (May 2008) to Revision A Page • Changed Condition in first TIMING REQUIREMENTS from 4.5 V to 3.1 V ......................................................................... 5 • Changed SCLK Low time MIN value from 9ns to 8ns and SCLK High time MIN value from 9ns to 8ns ............................. 5 • Changed Condition in second TIMING REQUIREMENTS from +4.5 V to + 3.1 V .............................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS8318IBDGSR VSSOP DGS 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8318IBDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8318IBDRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8318IBDGSR VSSOP DGS 10 2500 367.0 367.0 35.0 ADS8318IBDGST VSSOP DGS 10 250 210.0 185.0 35.0 ADS8318IBDRCR SON DRC 10 3000 338.1 338.1 20.6 ADS8318IBDRCT SON DRC 10 250 210.0 185.0 35.0 ADS8318IDGSR VSSOP DGS 10 2500 367.0 367.0 35.0 ADS8318IDGST VSSOP DGS 10 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.