Datasheet
1 2
15
16
CONVST
ACQUISITION
CONVERSION
ACQUISITION
SCLK
SDO #2
t
7
t
2
t
3
t
clkh
t
clkl
t
clk
17
18
31
32
#1-D15 #1-D14 #1-D1
#1-D0
#2-D15
#2-D14
#2-D1
#2-D0
SDO #1, SDI #2
#1-D15 #1-D14 #1-D1
#1-D0
t
8
t
cnv
t
cyc
t
acq
t
6
CONVST
SDO
SCLK
SDI
CONVST
SDO
SCLK
SDI SDI
CLK
CNV
ADS8318#1
DigitalHost
IRQ
ADS8318#2
ADS8318
SLAS568A –MAY 2008– REVISED MARCH 2011
www.ti.com
SDI and CONVST are low together. The rising edge of CONVST while SDI is low selects daisy chain mode and
the device samples the analog input and enters the conversion phase. It is necessary that SCLK is low at the
rising edge of CONVST so that the device does not generate a busy indicator at the end of the conversion. In
this mode CONVST continues to be high from the start of the conversion until all of the data bits are read. Once
started, conversion continues irrespective of the state of SCLK.
At the end of the conversion, every device in the chain initiates output of its conversion data starting with the
MSB bit. Further the next lower data bit is output on every falling edge of SCLK. While every device outputs its
data on the SDO pin, it also receives previous device data on the SDI pin (other than device #1) and stores it in
the shift register. The device latches incoming data on every falling edge of SCLK. SDO of the first device in the
chain goes low after the 16th falling edge of SCLK. All subsequent devices in the chain output the stored data
from the previous device in MSB first format immediately following their own data word.
It needs 16 × N clocks to read data for N devices in the chain.
Figure 54. Interface Timing Diagram, Daisy Chain Mode Without Busy Indicator
Daisy Chain Mode With Busy Indicator
Figure 55. Connection Diagram, Daisy Chain Mode With Busy Indicator (SDI = 0)
Refer to Figure 55 for the connection diagram. SDI for device 1 is wired to it's CONVST and CONVST for all the
devices in the chain are wired together. SDO of device 1 goes to SDI of device 2 and so on. SDO of the last
device in the chain goes to the digital host. In this mode there is no CS signal. On the rising edge of CONVST,
all of the device in the chain sample the analog input and enter the conversion phase. For the first device, SDI
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