Datasheet

AGND
+VA
218 W
218 W
55pF
55pF
4pF
4pF
+IN
-IN
DeviceinHoldMode
ADS8318
SLAS568A –MAY 2008– REVISED MARCH 2011 www.ti.com
APPLICATION INFORMATION
ANALOG INPUT
When the converter samples the input, the voltage difference between the +IN and -IN inputs is captured on the
internal capacitor array. The voltage on the +IN and –IN inputs individually is limited between GND –0.1 V and
V
ref
+ 0.1 V; where as the differential signal range [(+IN) – (–IN)] is 2V
ref
(–V
ref
to +V
ref
) with a common mode of
(V
ref
/2). This allows the input to reject small signals which are common to both the +IN and –IN inputs.
The (peak) input current through the analog inputs depends upon a number of factors: sample rate, input
voltage, and source impedance. The current into the ADS8318 charges the internal capacitor array during the
sample period. After this capacitance has been fully charged, there is no further input current. The source of the
analog input voltage must be able to charge the input capacitance (59 pF) to a 18-bit settling level within the
minimum acquisition time. When the converter goes into hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the +IN
and -IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, converter
linearity may not meet specifications.
Care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are
matched. If this is not observed, the two inputs could have different settling times. This may result in an offset
error, gain error, and linearity error which change with temperature and input voltage.
Figure 57. Input Equivalent Circuit
DRIVER AMPLIFIER CHOICE
The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031, OPA211. An
RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 5Ω and a
differential capacitor of 1nF is recommended. The input to the converter is a unipolar input voltage in the range 0
V to V
ref
. The minimum –3dB bandwidth of the driving operational amplifier can be calculated as:
f3db = (ln(2) × (n+2))/(2π × tACQ)
where n is equal to 16, the resolution of the ADC (in the case of the ADS8318). When t
ACQ
= 600 ns (minimum
acquisition time), the minimum bandwidth of the driving circuit is ~3 MHz (including RC following the driver OPA).
The bandwidth can be relaxed if the acquisition time is increased by the application.
Typically a low noise OPA with ten times or higher bandwidth is selected. The driving circuit bandwidth is
adjusted (to the required value) with a RC following the OPA. The OPA211 or THS4031 from Texas Instruments
is recommended for driving high-resolution high-speed ADCs.
DRIVER AMPLIFIER CONFIGURATIONS
Configuration for Unipolar Differential Input
It is better to use a unity gain, noninverting buffer configuration for a unipolar, differential input having a ±V
ref
signal range with V
ref
/2 common-mode. As explained before a RC following the OPA limits the input circuit
bandwidth just enough for 16-bit settling. Note higher bandwidth reduces the settling time (beyond what is
needed) but increases the noise in the ADC sampled signal, and hence the ADC output.
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