Datasheet

20pF
1.4V
I
ol
I
oh
500µA
500µA
From
SDO
0.8V
2V
t
DELAY
0.3 VBD
t
DELAY
0.7 VBD
2V
0.8V
ADS8318
SLAS568A –MAY 2008– REVISED MARCH 2011 www.ti.com
TIMING REQUIREMENTS
All specifications typical at –40°C to 85°C, +VA = 5 V, +3.1 V > +VBD ≥ 2.375 V
PARAMETER REF FIGURE MIN TYP MAX UNIT
SAMPLING AND CONVERSION RELATED
t
acq
Acquisition time 600 ns
Figure 46, Figure 48, Figure 50,
t
cnv
Conversion time 1400 ns
Figure 52
t
cyc
Time between conversions 2000 ns
t
1
Pulse width CONVST high Figure 46, Figure 48 10 ns
t
6
Pulse width CONVST low Figure 50, Figure 52, Figure 54 20 ns
I/O RELATED
t
clk
SCLK period 30 ns
t
clkl
SCLK low time 13 ns
Figure 46, Figure 48, Figure 50,
t
clkh
SCLK high time 13 ns
Figure 52, Figure 54, Figure 56
t
2
SCLK falling edge to data remains valid 5 ns
t
3
SCLK falling edge to next data valid delay 24 ns
t
en
CONVST or SDI low to MSB valid Figure 46, Figure 50 22 ns
CONVST or SDI high or last SCLK falling edge to SDO Figure 46, Figure 48, Figure 50,
t
dis
15 ns
3-state (CS mode) Figure 52
t
4
SDI valid setup time to CONVST rising edge 5 ns
Figure 50, Figure 52
t
5
SDI valid hold time from CONVST rising edge 5 ns
t
7
SCLK valid setup time to CONVST rising edge 5 ns
Figure 54
t
8
SCLK valid hold time from CONVST rising edge 5 ns
Figure 1. Load Circuit for Digital Interface Timing
Figure 2. Voltage Levels for Timing
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