Datasheet

1
2
3
4
5
10
9
8
7
6
REFIN
+VA
IN+
IN-
GND
+VBD
SDI
SCLK
SDO
CONVST
MSOP PACKAGE
(TOP VIEW)
1
2
3
4
5
10
9
8
7
6
(TOP VIEW)
SONPACKAGE
REFIN
+VA
IN+
IN-
GND
+VBD
SDI
SCLK
SDO
CONVST
-0.01
-0.009
-0.008
-0.007
-0.006
-0.005
-0.004
-0.003
-0.002
-0.001
4.5 4.75 5 5.25 5.5
GainError-%FSR
+VA -SupplyVoltage-V
+VBD=2.7V,
V =4.096V,
f =500KSPS,
T =30°C
ref
s
A
0.2
0.22
0.24
0.26
0.28
0.3
0.32
0.34
0.36
0.38
0.4
4.5 4.75 5 5.25 5.5
+VA -SupplyVoltage-V
OffsetError-mV
+VBD=2.7V,
V =4.096V,
f =500KSPS,
T =30°C
ref
s
A
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
2 2.5 3 3.5 4 4.5 5
V -ReferenceVoltage-V
ref
OffsetError-mV
+VA =5V
+VBD=2.7V,
f =500KSPS,
T =30°C
s
A
ADS8318
www.ti.com SLAS568A –MAY 2008–REVISED MARCH 2011
PIN ASSIGNMENTS
Terminal Functions
TERMINAL
I/O DESCRIPTION
NO. NAME
ANALOG PINS
1 REFIN I Reference (positive) input. Decouple with GND pin using 0.1-μF bypass capacitor and 10-μF storage
capacitor.
3 +IN I Noninverting analog signal input
4 –IN I Inverting analog signal input
I/O PINS
Convert input. It also functions as the CS input in 3-wire interface mode. Refer to Description and Timing
6 CONVST I
Diagrams sections for more details.
7 SDO O Serial data output.
8 SCLK I Serial I/O clock input. Data (on SDO o/p) is synchronized with this clock.
9 SDI I Serial data input. The SDI level at the start of a conversion selects the mode of operation such as CS or daisy
chain mode. It also serves as the CS input in 4-wire interface mode. Refer to Description and Timing
Diagrmas sections for more details.
POWER SUPPLY PINS
2 +VA – Analog power supply. Decoupled with GND pin.
5 GND – Device ground. Note this is a common ground pin for both analog power supply (+VA) and digital I/O supply
(+VBD).
10 +VBD – Digital I/O power supply. Decouple with GND pin.
TYPICAL CHARACTERISTICS
OFFSET ERROR GAIN ERROR OFFSET ERROR
vs vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE REFERENCE VOLTAGE
Figure 3. Figure 4. Figure 5.
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