Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External VSSOP 8

DESCRIPTION

The ADS8321 is a 16-bit sampling analog-to-digital con-

verter (ADC) with tested specifications over a 4.75V to

5.25V supply range. It requires very little power even when

operating at the full 100kHz data rate. At lower data rates,

the high speed of the device enables it to spend most of its

time in the power-down mode—the average power dissipa-

tion is less than 1mW at 10kHz data rate.

The ADS8321 also features a synchronous serial (SPI/SSI

compatible) interface, and a differential input. The refer-

ence voltage can be set to any level within the range of

500mV to V

/2.

Ultra-low power and small size make the ADS8321 ideal

for portable and battery-operated systems. It is also a

perfect fit for remote data acquisition modules, simulta-

neous multi-channel systems, and isolated data acquisi-

tion. The ADS8321 is available in an MSOP-8 package.

16-Bit, High Speed, MicroPower Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● BIPOLAR INPUT RANGE

● 100kHz SAMPLING RATE

● MICRO POWER:

4.5mW at 100kHz

1mW at 10kHz

● POWER DOWN: 3µA max

● MSOP-8 PACKAGE

● PIN-COMPATIBLE TO ADS7816 AND ADS7822

● SERIAL (SPI/SSI) INTERFACE

APPLICATIONS

● BATTERY OPERATED SYSTEMS

● REMOTE DATA ACQUISITION

● ISOLATED DATA ACQUISITION

● SIMULTANEOUS SAMPLING,

MULTI-CHANNEL SYSTEMS

● INDUSTRIAL CONTROLS

● ROBOTICS

● VIBRATION ANALYSIS

SAR

Serial

Interface

Comparator

ADS8321

S/H Amp

DCLOCK

OUT

CS/SHDN

+In

REF

–In

CDAC

ADS8321

SBAS123B – SEPTEMBER 1999 – REVISED SEPTEMBER 2004

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (19 pages)

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ADS8321 SBAS123B – SEPTEMBER 1999 – REVISED SEPTEMBER 2004 16-Bit, High Speed, MicroPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● BIPOLAR INPUT RANGE ● 100kHz SAMPLING RATE ● MICRO POWER: 4.5mW at 100kHz 1mW at 10kHz ● POWER DOWN: 3µA max ● MSOP-8 PACKAGE ● PIN-COMPATIBLE TO ADS7816 AND ADS7822 ● SERIAL (SPI/SSI) INTERFACE The ADS8321 is a 16-bit sampling analog-to-digital converter (ADC) with tested specifications over a 4.75V to 5.25V supply range.
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ABSOLUTE MAXIMUM RATINGS(1) VCC ....................................................................................................... +6V Analog Input ............................................................. –0.3V to (VCC + 0.3V) Logic Input ............................................................................... –0.3V to 6V Case Temperature ......................................................................... +100°C Junction Temperature ....................................................
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SPECIFICATIONS: +VCC = +5V At –40°C to +85°C, VREF = +2.5V, –In = 2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified. ADS8321E PARAMETER CONDITIONS MIN TYP RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range +In – (–In) +In –In –VREF –0.1 –0.1 REFERENCE INPUT Voltage Range Resistance ±0.018 ±2 ±0.006 ±0.2 ✻ ±0.05 ±0.05 +4.7V < VCC < 5.25V 100 2.9 ✻ 80 3 3.0 –0.3 4.0 ✻ ✻ ✻ –40 ✻ 5.25 5.25 1700 V GΩ GΩ µA µA µA V V V V ✻ ✻ ✻ ✻ ✻ ✻ ✻ 8.
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TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise specified. FREQUENCY SPECTRUM (8192 Point FFT, fIN = 10.03kHz, –0.3dB) INTEGRAL LINEARITY ERROR vs CODE (+25°C) 3 –20 2 Integral Linearity Error (LSB) 0 Amplitude (dB) –40 –60 –80 –100 –120 –140 –160 1 0 –1 –2 –3 –4 –5 –180 –6 0 10 20 30 40 50 0000H 4000H 7FF9H Frequency (kHz) DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) 2.5 1200 2.
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TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise specified. SIGNAL-TO-NOISE AND SIGNAL-TO-(NOISE + DISTORTION) vs INPUT FREQUENCY MAXIMUM SAMPLE RATE vs VCC 1000 90 SNR SNR and SINAD (dB) Sample Rate (kHz) 85 100 10 80 SINAD 75 70 1 65 1 2 3 4 5 0.
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TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise specified. CHANGE IN OFFSET vs TEMPERATURE 5.0 5.0 4.0 Change from +25°C (LSB) Change in BPZ (LSB) CHANGE IN BIPOLAR ZERO vs REFERENCE VOLTAGE 6.0 4.0 3.0 2.0 1.0 0 –1.0 –2.0 3.0 2.0 1.0 0 –1.0 –2.0 –3.0 –4.0 –3.0 –5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 –50 0 Reference Voltage (V) 100 COMMON-MODE REJECTION RATIO vs FREQUENCY CHANGE IN GAIN vs TEMPERATURE 5.0 90 4.
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THEORY OF OPERATION 2 • VREF peak-to-peak Single-Ended Input VREF peak-to-peak ADS821 Common Voltage VREF peak-to-peak Differential Input FIGURE 1. Methods of Driving the ADS8321—Single-Ended or Differential. 5 VCC = 5V 4.0 4 Single-Ended Input 3 2.8 2.2 2 1 0 –0.3 –1 0.0 0.5 1.0 1.5 2.0 2.5 VREF (V) FIGURE 2. Single-Ended Input—Common Voltage Range vs VREF. The analog input is bipolar and fully differential.
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different settling times. This may result in offset error, gain error, and linearity error which change with both temperature and input voltage. If the impedance cannot be matched, the errors can be lessened by giving the ADS8321 additional acquisition time. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, and source impedance. Essentially, the current into the ADS8321 charges the internal capacitor array during the sample period.
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AVERAGING The noise of the ADC can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/√n, where n is the number of averages. For example, averaging 4 conversion results will reduce the transition noise by 1/2 to ±0.25 LSBs. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low pass filter and decimate the output codes.
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DATA FORMAT The output data from the ADS8321 is in Binary Two’s Complement format as shown in Table II. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise.
PAGE 11
Supply Current (µA) 1000 TA = 25°C VCC = 5.0V VREF = 2.5V fCLK = 2.4MHz 100 10 1 0.1 1 10 100 Sample Rate (kHz) FIGURE 8. Maintaining fCLK at the Highest Possible Rate Allows Supply Current to Drop Linearly with Sample Rate. Supply Current (µA) 1000 100 10 TA = 25°C VCC = 5.0V VREF = 2.5V fCLK = 24 • fSAMPLE 1 0.1 1 10 100 Sample Rate (kHz) FIGURE 9. Scaling fCLK Reduces Supply Current Only Slightly with Sample Rate.
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power devices, to name a few. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter’s DCLOCK signal—as the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS8321 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the ADS8321 package as possible.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8321E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8321E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8321EB/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8321E/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS8321E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8321EB/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS8321EB/2K5 VSSOP DGK 8 2500 367.0 367.0 35.
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