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ADS8325

FEATURES DESCRIPTION

APPLICATIONS

SAR

Serial

Interface

Comparator

ADS8325

S/HAmp

DCLOCK

OUT

CS/SHDN

+IN

REF

-IN

CDAC

ADS8325

SBAS226C – MARCH 2002 – REVISED AUGUST 2007

16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling

ANALOG-TO-DIGITAL CONVERTER

• 16-Bits No Missing Codes

The ADS8325 is a 16-bit, sampling, Analog-to-Digital

(A/D) converter specified for a supply voltage range

• Very Low Noise: 3LSB

from 2.7V to 5.5V. It requires very little power, even

• Excellent Linearity: ± 1.5LSB typ

when operating at the full 100kHz data rate. At lower

• microPower:

data rates, the high speed of the device enables it to

– 4.5mW at 100kHz spend most of its time in the power-down mode. For

example, the average power dissipation is less than

– 1mW at 10kHz

1mW at a 10kHz data rate.

• MSOP-8 and SON-8 Packages (SON Package

The ADS8325 offers excellent linearity and very low

Size Same as 3x3 QFN)

noise and distortion. It also features a synchronous

• 16-Bit Upgrade to the 12-Bit ADS7816 and

serial (SPI/SSI compatible) interface and a differential

ADS7822

input. The reference voltage can be set to any level

• Pin-Compatible With the ADS7816 , ADS7822 ,

within the range of 2.5V to V

ADS7826 , ADS7827 , ADS7829 , and ADS8320

Low power and small size make the ADS8325 ideal

• Serial ( SPI™/SSI) Interfaces

for portable and battery-operated systems. It is also a

perfect fit for remote data acquisition modules,

simultaneous multichannel systems, and isolated

data acquisition. The ADS8325 is available in

• Battery-Operated Systems

MSOP-8 and SON-8 packages. The SON package

• Remote Data Acquisition

size is the same as a 3x3 QFN package.

• Isolated Data Acquisition

• Simultaneous Sampling, Multi-Channel

Systems

• Industrial Controls

• Robotics

• Vibration Analysis

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 SPI is a trademark of Motorola, Inc.

3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

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ADS8325 AD S8 32 5 AD S8 3 25 SBAS226C – MARCH 2002 – REVISED AUGUST 2007 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION 1 • • • • 23 • • • • 16-Bits No Missing Codes Very Low Noise: 3LSBPP Excellent Linearity: ±1.5LSB typ microPower: – 4.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 EQUIVALENT INPUT CIRCUIT VDD VDD C(SAMPLE) 40pF RON 50W ANALOG IN VDD Shut-Down Switch 20pF I/O REF 5kW GND GND GND Diode Turn-On Voltage: 0.35V Equivalent Reference Equivalent Analog Input Circuit Input Circuit Equivalent Digital Input/Output Circuit RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted) MIN Supply voltage, GND to VDD Low-voltage levels 2.7 5V logic levels 4.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS: VDD = +5 V (continued) Over recommended operating free-air temperature at –40°C to +85°C, VREF = 5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS: VDD = +2.7V Over recommended operating free-air temperature at –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8325I PARAMETER TEST CONDITIONS MIN TYP ADS8325IB MAX MIN VREF 0 0.5 –0.3 TYP MAX UNIT VREF V ANALOG INPUT Full-scale range FSR +IN – (–IN) 0 Operating common-mode signal –0.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 ELECTRICAL CHARACTERISTICS: VDD = +2.7V (continued) Over recommended operating free-air temperature at –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 × fSAMPLE, unless otherwise noted. ADS8325I PARAMETER TEST CONDITIONS MIN High-level output voltage VOH VDD = 2.7V, IOH = –100μA VDD – 0.2 Low-level output voltage VOL VDD = 2.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 PIN CONFIGURATIONS DGK PACKAGE MSOP (TOP VIEW) REF 1 +IN 2 8 +VDD 7 DCLOCK ADS8325 -IN 3 6 DOUT GND 4 5 CS/SHDN DRB PACKAGE(1) SON (TOP VIEW) REF 1 +IN 2 8 +VDD 7 DCLOCK 6 DOUT 5 CS/SHDN ADS8325 (1) -IN 3 GND 4 (Thermal Pad) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TIMING INFORMATION tCYC CS/SHDN Sample Power Down Conversion tSUCS DCLOCK tCSD Use positive clock edge for data transfer Hi-Z DOUT 0 tSMPL B7 B15 B14 B13 B12 B11 B10 B9 B8 (MSB) tCONV B6 B5 B4 B3 B2 Hi-Z (1) B1 B0 (LSB) NOTE: (1) A minimum of 22 clock cycles are required for 16-bit conversion; 24 clock cycles are shown.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TIMING INFORMATION (continued) Table 1. Timing Characteristics SYMBOL DESCRIPTION MIN TYP 4.5 MAX 5.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TYPICAL CHARACTERISTICS: VDD = +5V At TA = +25°C, VDD = +5V, VREF = +5V, fSAMPLE = 100kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. 3 3 2 2 1 1 0 -1 -2 -2 4000H 8000H C000H -3 0000H FFFFH 4000H C000H FFFFH Output Code Figure 2. Figure 3. FREQUENCY SPECTRUM (8192 Point FFT, fIN = 1.0132kHz, –0.2 dB) FREQUENCY SPECTRUM (8192 Point FFT, fIN = 10.0022kHz, –0.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V, fSAMPLE = 100kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL PEAK-TO-PEAK NOISE FOR A DC INPUT vs REFERENCE VOLTAGE 200 fIN = 1.0132kHz 90 100 Peak-to-Peak Noise (LSB) Signal-to-Noise + Distortion (dB) 100 80 70 60 50 40 30 10 20 10 1 -80 -70 -60 -50 -40 -30 -20 -10 0.1 0 Figure 8. Figure 9.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V, fSAMPLE = 100kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE Supply Current (mA) 1.1 1.0 0.9 0.8 0.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, VDD = 2.7V, VREF = 2.5V, fSAMPLE = 100kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE 3 3 2 2 1 1 DLE (LSBS) 0 0 -1 -1 -2 -2 -3 0000H 4000H 8000H C000H -3 0000H FFFFH 4000H 8000H FFFFH Figure 15. Figure 16. FREQUENCY SPECTRUM (8192 Point FFT, fIN = 1.0132kHz, –0.2 dB) FREQUENCY SPECTRUM (8192 Point FFT, fIN = 10.0022kHz, –0.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, VDD = 2.7V, VREF = 2.5V, fSAMPLE = 100kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY fIN = 1.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 THEORY OF OPERATION ANALOG INPUT The ADS8325 is a classic Successive Approximation Register (SAR) Analog-to-Digital (A/D) converter. The architecture is based on capacitive redistribution that inherently includes a sample-andhold function. The converter is fabricated on a 0.6μ CMOS process.
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ADS8325 www.ti.com Common-Mode Voltage Range (V) SBAS226C – MARCH 2002 – REVISED AUGUST 2007 1 VDD = 5V 0.5 0 -0.3 -1 2 2.5 3 4 6 4.8 5 VREF (V) Figure 28. +IN Analog Input: Common-Mode Voltage Range vs VREF Delta Relative to VCM = 0V (LSB) 60 50 VDD = 5V VREF = 4V Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the –IN input should not drop below GND – 0.3V or exceed GND + 0.5V.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 50W 50W 40pF +IN OPA365 50W 100pF 50W 40pF +IN OPA365 100pF ADS8325 -IN ADS8325 1nF 50W 40pF 50W -IN OPA365 50W 40pF 100pF Single-Ended Differential Figure 31. Single-Ended and Differential Methods of Interfacing the ADS8325 The external reference sets the analog input range. The ADS8325 will operate with a reference in the range of 2.5V to VDD. There are several important implications to this.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Due to the lower LSB size, the converter will also be more sensitive to external sources of error, such as nearby digital signals and electromagnetic interference. The equivalent input circuit for the reference voltage is presented in Figure 33.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 AVERAGING SERIAL INTERFACE The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise will be reduced by a factor of 1/√n, where n is the number of averages. For example, averaging four conversion results will reduce the transition noise from ±0.5LSB to ±0.25LSB. Averaging should only be used for input signals with frequencies near DC.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 1111 1111 1111 1111 65535 1111 1111 1111 1111 65534 1111 1111 1111 1111 65533 1000 0000 0000 0001 32769 1000 0000 0000 0000 32768 Step Digital Output Code Straight Binary 32767 0111 1111 1111 1111 0000 0000 0000 0010 2 0000 0000 0000 0001 1 0000 0000 0000 0000 0 2.499962V VZ = VCM = 0V 2.500038V VFS = VCM + VREF = 5V 38.15mV VFS - 1LSB = 4.999924V VMS = VCM + VREF/2 = 2.5V 76.29mV 4.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 POWER DISSIPATION In addition, the ADS8325 is in power-down mode under two conditions: when the conversion is complete and whenever CS is HIGH (see the Timing Information section). Ideally, each conversion should occur as quickly as possible, preferably at a 2.4MHz clock rate. This way, the converter spends the longest possible time in the power-down mode.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8325 circuitry. This will be particularly true if the reference voltage is low and/or the conversion rate is high. At a 100kHz conversion rate, the ADS8325 makes a bit decision every 416ns.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 APPLICATION CIRCUITS high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of noise. Operational amplifiers and voltage reference are connected to analog power supply, AVDD. Figure 39 shows a basic data acquisition system. The ADS8325 input range is connected to 2.5V or 4.096V.
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ADS8325 www.ti.com SBAS226C – MARCH 2002 – REVISED AUGUST 2007 Revision History Changes from Revision B (June 2007) to Revision C .................................................................................................... Page • • Changed note for DRB package............................................................................................................................................ 7 Changed second timing diagram from the top; moved Hi-Z to span the entire range of tSMPL .........
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2007 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com Device 6-Aug-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8325IBDGKR DGK 8 MLA 330 12 5.2 3.3 1.6 12 12 NONE ADS8325IBDGKT DGK 8 MLA 330 12 5.2 3.3 1.6 12 12 NONE ADS8325IBDRBR DRB 8 TUA 330 12 3.3 3.3 1.1 8 12 Q2 ADS8325IBDRBT DRB 8 TUA 330 12 3.3 3.3 1.1 8 12 Q2 ADS8325IDGKR DGK 8 MLA 330 12 5.2 3.3 1.
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PACKAGE MATERIALS INFORMATION www.ti.
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This package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS8325IBDGKR VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8325IBDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8325IBDRBR SON DRB 8 2500 330.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8325IBDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8325IBDGKT VSSOP DGK 8 250 210.0 185.0 35.0 ADS8325IBDRBR SON DRB 8 2500 367.0 367.0 35.0 ADS8325IBDRBT SON DRB 8 250 210.0 185.0 35.0 ADS8325IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8325IDGKT VSSOP DGK 8 250 210.0 185.0 35.
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