Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 16

REF−

+IN

REF+

SDI

SCLK

SDO

CDAC

SAR

COMPARATOR

OUTPUT

LATCH

and

3−STATE

DRIVER

CONVERSION

and

CONTROL

LOGIC

−IN

+IN1

+IN0

COM

OSC

ADS8328 ADS8327

FS/CS

CONVST

EOC/INT/CDI

ADS8327

ADS8328

www.ti.com

SLAS415E – APRIL 2006– REVISED JANUARY 2011

LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL

CONVERTERS WITH SERIAL INTERFACE

Check for Samples: ADS8327, ADS8328

FEATURES

APPLICATIONS

• Communications

• 2.7-V to 5.5-V Analog Supply, Low Power:

• Transducer Interface

– 10.6 mW (500 kHz, +VA = 2.7 V,

• Medical Instruments

+VBD = 1.8 V)

• Magnetometers

• 500-kHz Sampling Rate

• Industrial Process Control

• Excellent DC Performance

• Data Acquisition Systems

– ±1.5 LSB Typ, ±2 LSB Max INL

• Automatic Test Equipment

– ±0.6 LSB Typ, ±1 LSB Max DNL

– 16-Bit NMC Over Temperature

DESCRIPTION

– ±0.5 mV Max Offset Error at 2.7 V

The ADS8327 is a low power, 16-bit, 500-kSPS

– ±1 mV Max Offset Error at 5 V

analog-to-digital converter with a unipolar input. The

• Excellent AC Performance at f

= 10 kHz with

device includes a 16-bit capacitor-based SAR A/D

converter with inherent sample and hold.

91 dB SNR, 100 dB SFDR, –96 dB THD

• Built-In Conversion Clock (CCLK)

The ADS8328 is based on the same core and

includes a 2-to-1 input MUX with programmable

• 1.65 V to 1.5×(+VA) I/O Supply

option of TAG bit output. Both the ADS8327 and

– SPI/DSP Compatible Serial

ADS8328 offer a high-speed, wide voltage serial

– SCLK up to 50 MHz

interface and are capable of chain mode operation

when multiple converters are used.

• Comprehensive Power-Down Modes:

– Deep Power-Down

These converters are available in a 16-lead TSSOP

or 4x4 QFN packages and are fully specified for

– Nap Power-Down

operation over the industrial –40°C to +85°C

– Auto Nap Power-Down

temperature range.

• Unipolar Input Range: 0 V to V

REF

Table 1. Low Power, High-Speed SAR Converter

• Software Reset

Family

• Global CONVST (Independent of CS)

Type/Speed 500 kHz 1 MHz

• Programmable Status/Polarity EOC/INT

Single ADS8327 ADS8329

• 16-Pin 4×4 QFN or 16-Pin TSSOP Packages

16 Bit Pseudo-Diff

Dual ADS8328 ADS8330

• Multi-Chip Daisy Chain Mode

• Programmable TAG Bit Output

• Auto/Manual Channel Select Mode

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (50 pages)

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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE Check for Samples: ADS8327, ADS8328 FEATURES APPLICATIONS • • • • • • • • 1 • • • • • • • • • • • • • • 2.7-V to 5.5-V Analog Supply, Low Power: – 10.6 mW (500 kHz, +VA = 2.7 V, +VBD = 1.8 V) 500-kHz Sampling Rate Excellent DC Performance – ±1.5 LSB Typ, ±2 LSB Max INL – ±0.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range, unless otherwise noted. (1) UNIT Voltage +IN to AGND –0.3 V to +VA + 0.3 V –IN to AGND –0.3 V to +VA + 0.3 V –0.3 V to 7 V +VA to AGND Voltage range +REF to AGND –0.3 V to +VA + 0.3 V –REF to AGND –0.3 V to +0.3 V +VBD to BDGND –0.3 V to 7 V AGND to BDGND –0.3 V to 0.3 V Digital input voltage to BDGND –0.3 V to +VBD + 0.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com SPECIFICATIONS TA = –40°C to 85°C, +VA = 2.7 V to 3.6 V, +VBD = 1.65 V to 1.5 × (+VA), VREF = 2.5 V, and fSAMPLE = 500 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V ANALOG INPUT Full-scale input voltage (1) +IN – (–IN) or (+INx – COM) Absolute input voltage 0 +VREF +IN, +IN0, +IN1 AGND – 0.2 +VA + 0.2 –IN or COM AGND – 0.2 AGND + 0.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 2.7 V to 3.6 V, +VBD = 1.65 V to 1.5 × (+VA), VREF = 2.5 V, and fSAMPLE = 500 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS (4) THD Total harmonic distortion SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion SFDR Spurious-free dynamic range –98 VIN = 2.5 VPP at 10 kHz VIN = 2.5 VPP at 100 kHz –83.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com SPECIFICATIONS TA = –40°C to 85°C, +VA = 4.5 V to 5.5 V, +VBD = 1.65 V to 5.5 V, VREF = 4.096 V, and fSAMPLE = 500 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V ANALOG INPUT Full-scale input voltage (1) Absolute input voltage +IN – (–IN) or (+INx – COM) 0 +VREF +IN, +IN0, +IN1 AGND – 0.2 +VA + 0.2 –IN or COM AGND – 0.2 AGND + 0.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 4.5 V to 5.5 V, +VBD = 1.65 V to 5.5 V, VREF = 4.096 V, and fSAMPLE = 500 kHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC CHARACTERISTICS VIN = 4.096 VPP at 10 kHz THD Total harmonic distortion (4) SNR Signal-to-noise ratio SINAD Signal-to-noise + distortion SFDR Spurious-free dynamic range -96 VIN = 4.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = 2.7 v, +VBD = 1.8 V (1) (2) PARAMETER fCCLK Frequency, conversion clock, CCLK MIN External, fCCLK = 1/2 fSCLK 0.5 Internal fCCLK = 1/2 fSCLK 10.5 TYP MAX UNIT 10.5 MHz 11 12.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TIMING CHARACTERISTICS All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (1) (2) PARAMETER fCCLK Frequency, conversion clock, CCLK MIN External, fCCLK = 1/2 fSCLK 0.5 Internal fCCLK = 1/2 fSCLK 10.9 TYP MAX UNIT 10.5 MHz 12 12.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com ADS8327 Terminal Functions NAME NO. I/O DESCRIPTION TSSOP QFN AGND 5 15 – Analog ground BDGND 14 8 – Interface ground CONVST 9 3 I Freezes sample and hold, starts conversion with next rising edge of internal clock O Status output. If programmed as EOC, this pin is low (default) when a conversion is in progress.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com MANUAL TRIGGER / READ While Sampling (use internal CCLK, EOC and INT polarity programmed as active low) Nth Nth tCONV = 18 CCLKs tSAMPLE1 = 3 CCLKs min INT (active low) tSAMPLE1 = 3 CCLKs min th(CSR-EOS) th(CSF-EOC) th(CSF-EOS) EOS twL(CONVST) EOC EOC (active low) EOS EOC CONVST th(CSF-EOC) tsu(CSF-EOC) tsu(CSF-EOS) CS/FS 1 SCLK 1 . . . . . . . . . . . . . . . . . . . .
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com MANUAL TRIGGER / READ While Converting (use internal CCLK, EOC and INT polarity programmed as active low) N + 1st Nth Nth EOC (active low) EOS EOC twL(CONVST) EOS CONVST tCONV = 18 CCLKs N + 1st tSAMPLE1 = 3 CCLKs min INT (active low) th(CSF-EOS) tsu(CSR-EOS) tsu(CSF-EOS) CS/FS tsu(CSF-EOC) th(CSF-EOC) SCLK 1 1 . . . . . . . . . . . . . . . . . . . .
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 1 2 www.ti.com 3 4 5 6 14 7 15 16 SCLK tsu(CSF−SCLK1F) tc(SCLK) twH(SCLK) twL(SCLK) CS/FS tsu(16thSCLK−CSR) td(SCLKF−SDOINVALID) td(CSR−SDOZ) td(SCLKF−SDOVALID) td(CSF−SDOVALID) SDO Hi−Z MSB−1 MSB−2 MSB−3 MSB−4 MSB MSB−5 MSB−6 LSB+2 LSB+1 LSB th(SDI−SCLKF) MSB SDI MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6 LSB+2 LSB+1 LSB tsu(SDI−SCLKF) Figure 5.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS At –40°C to 85°C, VREF (REF+ – REF–) = 4.096 V when +VA = +VBD = 5 V or VREF (REF+ – REF–) = 2.5 V when +VA = +VBD = 2.7 V, fSCLK = 21 MHz, fI = DC for DC curves, and fI = 100 kHz for AC curves, unless otherwise noted. CROSSTALK vs FREQUENCY DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 0.9 110 1.8 105 1.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) INTEGRAL NONLINEARITY vs EXTERNAL CLOCK FREQUENCY OFFSET VOLTAGE vs FREE-AIR TEMPERATURE 2 OFFSET VOLTAGE vs SUPPLY VOLTAGE 1 1 0.8 0.8 +VA = 2.7 V 1.5 Max 0.5 0 -0.5 -1 0.6 +VA = 5 V 0.4 0.2 5 10 15 20 External Clock Frequency - MHz 25 3.2 3.7 4.2 4.7 +VA - Supply Voltage - V 5.2 Figure 14. Figure 15.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SPURIOUS-FREE DYNAMIC RANGE vs INPUT FREQUENCY SNR - Signal-To-Noise Ratio - dB 100 +VA = 5 V 95 +VA = 2.7 V 90 85 5V 84 80 76 72 0 60 80 20 40 fi - Input Frequency - kHz 0 100 1 2 3 Full Scale Range - V 4 2.7 V 5V 84 80 76 72 5 0 1 2 3 Full Scale Range - V 4 5 Figure 22. Figure 23. Figure 24.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFECTIVE NUMBER OF BITS vs FREE-AIR TEMPERATURE INTERNAL CLOCK FREQUENCY vs SUPPLY VOLTAGE INTERNAL CLOCK FREQUENCY vs FREE-AIR TEMPERATURE 14.7 +VA = 5 V, 100 kHz Input 14.5 12 Internal Clock Frequency - MHz 14.9 Internal Clock Frequency - MHz 11.8 11.6 11.4 11.2 11.0 2.7 14.3 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 3.2 11.2 3.7 4.2 4.7 5.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) ANALOG SUPPLY CURRENT vs FREE-AIR TEMPERATURE 0.4 Analog Supply Current - mA NAP Mode +VA = 5 V 0.3 +VA = 2.7 0.2 0.1 0 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 80 Figure 40. INL DNL 2 3 fi = 500 kSPS, +VA = 5 V, Vref = 4.096 V 2.5 2 fi = 500 kSPS, +VA = 5 V, Vref = 4.096 V 1.5 1.5 1 1 DNL - Bits INL - Bits 0.5 0.5 0 -0.5 0 -0.5 -1 -1 -1.5 -2 -1.5 -2.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) FFT FFT 0 0 1 kHz Input,+VA = 2.7 V, Vref = 2.5 V, fs = 500 kSPS -20 -40 -40 Amplitude - dB Amplitude - dB 10 kHz Input,+VA = 2.7 V, Vref = 2.5 V, fs = 500 kSPS -20 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 50 100 150 f - Frequency - kHz 200 250 0 50 Figure 45. 100 150 f - Frequency - kHz FFT 200 250 FFT 0 100 kHz Input, +VA = 2.7 V, Vref = 2.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) FFT FFT 0 0 10 kHz Input,+VA = 5 V, Vref = 4.096 V, fs = 500 kSPS 100 kHz Input,+VA = 5 V, Vref = 4.096 V, fs = 500 kSPS -20 -40 -40 -60 -60 Amplitude - dB Amplitude - dB -20 -80 -100 -80 -100 -120 -120 -140 -140 -160 -160 0 50 100 150 f - Frequency - kHz 200 250 0 50 Figure 49. 100 150 f - Frequency - kHz 200 250 Figure 50.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Device in Hold Mode 40 pF 150 W +IN 4 pF +VA AGND 4 pF 40 pF 150 W −IN AGND Figure 51. Input Equivalent Circuit Driver Amplifier Choice The analog input to the converter needs to be driven with a low noise, op-amp like the THS4031 or OPA365 . An RC filter is recommended at the input pins to low-pass filter the noise from the source. Two resistors of 20Ω and a capacitor of 470 pF is recommended.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com 5V ADS8327 +VA 1 VDC 20 W THS4031 Input Signal (-2V to 2 V) +IN 600 W 470 pF -IN 600 W 20 W Figure 53. Bipolar Input Drive Configuration REFERENCE The ADS8327/28 can operate with an external reference with a range from 0.3 V to 4.2 V. A clean, low noise, well-decoupled reference voltage on this pin is required to ensure good performance of the converter.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Manual Channel Select Mode The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command register (CMR). This cycle time can be as short as 4 serial clocks (SCLK). Auto Channel Select Mode Channel selection can also be done automatically if auto channel select mode is enabled. This is the default channel select mode. The dual channel converter, ADS8328, has a built-in 2-to-1 MUX.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Power-Down Modes The ADS8327/28 has a comprehensive built-in power-down feature. There are three power-down modes: Deep power-down mode, Nap power-down mode, and auto nap power-down mode. All three power-down modes are enabled by setting the related CFR bits. The first two power-down modes are activated when enabled. A wakeup command, 1011b, can resume device operation from a power-down mode.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Deep Power-Down Mode Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in deep power-down mode, all blocks except the interface are in power-down. The external SCLK is blocked to the analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this mode, supply current falls from 5 mA to 6 nA in 100 ns.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com EOS EOC EOS Converter State N+1 Converter State EOC N CONVST N+1 −th Sampling N −th Conversion N+1 −th Conversion Read While Converting 20 ns MIN 1 CCLK MIN CS (For Read Result) Read N−1 −th Result Read While Sampling 0 ns MIN 20 ns MIN CS (For Read Result) Read N −th Result Figure 56.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Internal Register The internal register consists of two parts, 4 bits for the command register (CMR) and 12 bits for configuration data register (CFR). Table 4.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com READING THE CONFIGURATION REGISTER The host processor can read back the value programmed in the CFR by issuing command 1100b. The timing is similar to reading a conversion result except CONVST is not used and there is no activity on the EOC/INT pin. The CFR value read back contains the first four MSBs of conversion data plus valid 12-bit CFR contents. Table 5.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com NOTE Whenever SDO is not in 3-state (when FS/CS is low and SCLK is running), a portion of the conversion result is output at the SDO pin. The number of bits depends on how many SCLKs are supplied. For example, a manual select channel command cycle requires 4 SCLKs, therefore 4 MSBs of the conversion result are output at SDO. The exception is SDO outputs all 1s during the cycle immediately after any reset (POR or software reset).
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com When multiple converters are used in chain mode, the first converter is configured in regular mode while the rest of the converters downstream are configured in chain mode. When a converter is configured in chain mode, the CDI input data goes straight to the output register, therefore the serial input data passes through the converter with a 16 SCLK (if the TAG feature is disabled) or a 24 SCLK delay, as long as CS is active.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com INT #1 (active low) Nth EOS EOC #1 (active low) EOC CONVST #1, CONVST #2, CONVST #3 EOS Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC, and INT polarity programmed as active low) CS held low during the N times 16 bits transfer cycle.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com Cascaded Manual Trigger/Read While Sampling (Use internal CCLK, EOC active low and INT active low) CS held low during the N times 16 bits transfer cycle. Note : old data shown. INT #1 (active low) Nth EOS EOC #1 (active low) EOC CONVST #2 = 1 EOS CONVST #1, CONVST #3 tSAMPLE1 = 3 CCLKs min tCONV = 18 CCLKs td(CSR-EOS) = 20 ns min CS/FS #1 SCLK #1, SCLK #2, SCLK #3 1 . . . . . . . . . . . . . . . . . .16 1 . . . . . . . .
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com SCLK skew between converters and data path delay through the converters configured in chain mode can affect the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the devices are configured in chain mode. ADS 8327 # 3 CDI SDO Logic D Delay < = 8 .3 ns Logic Delay Plus PAD 2.7 ns Serial data output Logic Delay Plus PAD 8.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com When the device is powered up, the POR sets the device in default mode when AVDD reaches 1.5 V. When the device is powered down, the POR circuit requires AVDD to remain below 125 mV for a duration of at least 350 ms to ensure proper discharging of internal capacitors and to correct the behavior of the device when powered up again.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com APPLICATION INFORMATION TYPICAL CONNECTION Analog +5 V 4.7 mF AGND Ext Ref Input 10 mF Analog Input AGND +VA REF+ REF− AGND IN+ IN− Host Processor FS/CS SDO SDI SCLK Interface Supply +1.8 V ADS8327 BDGND CONVST 4.7 mF EOC/INT +VBD Figure 66.
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ADS8327 ADS8328 SLAS415E – APRIL 2006 – REVISED JANUARY 2011 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (June 2009) to Revision E Page • Updated Figure 60 .............................................................................................................................................................. 33 • Updated Figure 61 ................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) ADS8328IRSATG4 ACTIVE Package Type Package Pins Package Drawing Qty QFN RSA 16 250 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-2-260C-1 YEAR (4) -40 to 85 ADS 8328I A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8327IBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 ADS8327IBRSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 ADS8327IBRSAT QFN RSA 16 250 180.0 12.4 4.3 4.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8327IBPWR ADS8327IBRSAR TSSOP PW 16 2000 367.0 367.0 35.0 QFN RSA 16 3000 338.1 338.1 20.6 ADS8327IBRSAT QFN RSA 16 250 210.0 185.0 35.0 ADS8327IPWR TSSOP PW 16 2000 367.0 367.0 35.0 ADS8327IRSAR QFN RSA 16 3000 338.1 338.1 20.6 ADS8327IRSAT QFN RSA 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.