Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External TSSOP 24

SDI

SCLK

SDO

CDAC

SAR

Comparator

Output

Latch

and

3-State

Driver

Conversion

and

Control

Logic

FS/CS

CONVST

EOC/INT/CDI

RESET

REF+

ADCINMUXOUT

IN[0:3]

IN[0:7]

COM

REF-

ADS8331

ADS8332

www.ti.com

SBAS363C –DECEMBER 2009–REVISED MAY 2012

Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input

ANALOG-TO-DIGITAL CONVERTERS with Serial Interface

Check for Samples: ADS8331, ADS8332

FEATURES

DESCRIPTION

The ADS8331 is a low-power, 16-bit, 500k samples-

234

• Low-Power, Flexible Supply Range:

per-second (SPS) analog-to-digital converter (ADC)

– 2.7V to 5.5V Analog Supply

with a unipolar, 4-to-1 multiplexer (mux) input. The

– 8.7mW (250kSPS in Auto-Nap Mode,

device includes a 16-bit capacitor-based successive

VA = 2.7V, VBD = 1.65V)

approximation register (SAR) ADC with inherent

sample and hold.

– 14.2mW (500kSPS, VA = 2.7V, VBD = 1.65V)

The ADS8332 is based on the same core and

• Up to 500kSPS Sampling Rate

includes a unipolar 8-to-1 input mux. Both devices

• Excellent DC Performance:

offer a high-speed, wide-voltage serial interface and

– ±1.2 LSB Typ, ±2 LSB Max INL at 2.7V

are capable of daisy-chain operation when multiple

– ±0.6 LSB Typ, –1.0/1.5 LSB Max DNL at 2.7V

converters are used.

– 16-Bit NMC Over Temperature

These converters are available in 24-pin, 4x4 QFN

and 24-pin TSSOP packages and are fully specified

• Excellent AC Performance at 5V, f

= 1kHz:

for operation over the industrial –40°C to +85°C

– 91.5dB SNR, 101dB SFDR, –100dB THD

temperature range.

• Flexible Analog Input Arrangement:

– On-Chip 4-/8-Channel Mux with Breakout

Low-Power, High-Speed, SAR Converter Family

RESOLUTION/TYPE CHANNELS 500kSPS 1MSPS

– Auto/Manual Channel Select and Trigger

1 ADS8327 ADS8329

• Other Hardware Features:

2 ADS8328 ADS8330

– On-Chip Conversion Clock (CCLK)

16-Bit Pseudo-Diff

4 ADS8331 —

– Software/Hardware Reset

8 ADS8332 —

– Programmable Status/Polarity EOC/INT

1 — ADS7279

14-Bit Pseudo-Diff

– Daisy-Chain Mode

2 — ADS7280

– Global CONVST (Independent of CS)

1 — ADS7229

12-Bit Pseudo-Diff

– Deep, Nap, and Auto-Nap Powerdown

2 — ADS7230

Modes

BLANKSPACE

– SPI™/DSP Compatible Serial Interface

– Separate I/O Supply: 1.65V to VA

Functional Block Diagram

– SCLK up to 40MHz (VA = VBD = 5V)

• 24-Pin 4x4 QFN and 24-Pin TSSOP Packages

APPLICATIONS

• Communications

• Transducer Interfaces

• Medical Instruments

• Magnetometers

• Industrial Process Control

• Data Acquisition Systems

• Automatic Test Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TMS320 is a trademark of Texas Instruments.

3SPI is a trademark of Motorola, Inc..

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (46 pages)

PAGE 1
ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 Low-Power, 16-Bit, 500kSPS, 4-/8-Channel Unipolar Input ANALOG-TO-DIGITAL CONVERTERS with Serial Interface Check for Samples: ADS8331, ADS8332 FEATURES DESCRIPTION • Low-Power, Flexible Supply Range: – 2.7V to 5.5V Analog Supply – 8.7mW (250kSPS in Auto-Nap Mode, VA = 2.7V, VBD = 1.65V) – 14.2mW (500kSPS, VA = 2.7V, VBD = 1.65V) • Up to 500kSPS Sampling Rate • Excellent DC Performance: – ±1.2 LSB Typ, ±2 LSB Max INL at 2.7V – ±0.
PAGE 2
ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS: VA = 2.7V At TA = –40°C to +85°C, VA = 2.7V, VBD = 1.65V to 2.7V, VREF = 2.5V, and fSAMPLE = 500kSPS, unless otherwise noted. ADS8331I, ADS8332I PARAMETER TEST CONDITIONS MIN TYP ADS8331IB, ADS8332IB MAX MIN VREF TYP MAX UNIT ANALOG INPUT Full-scale input voltage (1) Absolute input voltage INX – COM, ADCIN – COM 0 VREF V INX, ADCIN AGND – 0.2 0 VA + 0.2 AGND – 0.2 VA + 0.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: VA = 2.7V (continued) At TA = –40°C to +85°C, VA = 2.7V, VBD = 1.65V to 2.7V, VREF = 2.5V, and fSAMPLE = 500kSPS, unless otherwise noted. ADS8331I, ADS8332I PARAMETER TEST CONDITIONS ADS8331IB, ADS8332IB MIN TYP MAX MIN TYP MAX UNIT 10.5 11 12.2 10.5 11 12.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS: VA = 5V At TA = –40°C to +85°C, VA = 5V, VBD = 1.65V to 5V, VREF = 4.096V, and fSAMPLE = 500kSPS, unless otherwise noted. ADS8331I, ADS8332I PARAMETER TEST CONDITIONS MIN TYP ADS8331IB, ADS8332IB MAX MIN VREF TYP MAX UNIT ANALOG INPUT Full-scale input voltage (1) Absolute input voltage INX – COM, ADCIN – COM 0 VREF V INX, ADCIN AGND – 0.2 0 VA + 0.2 AGND – 0.2 VA + 0.2 V COM AGND – 0.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: VA = 5V (continued) At TA = –40°C to +85°C, VA = 5V, VBD = 1.65V to 5V, VREF = 4.096V, and fSAMPLE = 500kSPS, unless otherwise noted. ADS8331I, ADS8332I PARAMETER TEST CONDITIONS ADS8331IB, ADS8332IB MIN TYP MAX MIN TYP MAX UNIT 10.9 11.5 12.6 10.9 11.5 12.6 MHz 40 MHz 21 MHz 4.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 TIMING CHARACTERISTICS: VA = 2.7V At TA = –40°C to +85°C, VA = 2.7V, and VBD = 1.65V, unless otherwise noted. PARAMETER (1) (2) TEST CONDITIONS External, fCCLK = 1/2 fSCLK MIN TYP 0.5 MAX UNIT 10.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com TIMING CHARACTERISTICS: VA = 5V At TA = –40°C to +85°C, and VA = VBD = 5V, unless otherwise noted.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 TIMING DIAGRAMS tWL1 CONVST EOC (active low) tSU2 tH1 tSU5 CS tSCLK SCLK tD1 SDO High-Z MSB MSB - 1 MSB - 2 MSB - 3 tD3 SDI LSB + 1 tD2 LSB TAG2 X X TAG1 tD4 TAG0 '0' High-Z '0' tSU4 '1' '1' '0' X '1' X X X X tH3 Figure 1.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com TIMING DIAGRAMS (continued) CS tH1 EOC (active low) tD5 INT (active low) Figure 4.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 ADS8331 PIN DESCRIPTIONS PIN NO. TSSOP QFN I/O ADCIN NAME 21 18 I ADC input AGND 20 17 – Analog ground DGND 14 11 – Digital interface ground COM 23 20 I Common ADC input (usually connected to AGND) CONVST 15 12 I Conversion start. Freezes sample and hold, starts conversion. EOC/INT/CDI 9 6 O/O/I DESCRIPTION Status output.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DC Performance At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V, fSCLK = 21MHz, and fSAMPLE = 500kSPS, unless otherwise noted. INTEGRAL LINEARITY ERROR vs CODE 3 INTEGRAL LINEARITY ERROR vs CODE 3 VA = VBD = 2.7V VREF = 2.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: DC Performance (continued) At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V, fSCLK = 21MHz, and fSAMPLE = 500kSPS, unless otherwise noted. ANALOG SUPPLY CURRENT vs SAMPLING RATE IN AUTO-NAP MODE DEEP POWER-DOWN CURRENT vs TEMPERATURE 120 8 VA = VBD = 5.0V VREF = 4.096V 6 IA (mA) Deep Power-Down Current (nA) 7 5 4 3 VA = VBD = 2.7V VREF = 2.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: DC Performance (continued) At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V, fSCLK = 21MHz, and fSAMPLE = 500kSPS, unless otherwise noted. CHANGE IN DIGITAL SUPPLY CURRENT vs TEMPERATURE CHANGE IN INTERNAL CLOCK FREQUENCY vs TEMPERATURE 150 D Frequency (kHz relative to +25°C) 1.0 DIBD (mA relative to +25°C) 0.8 0.6 VA = VBD = 2.7V VREF = 2.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: AC Performance At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V, fSCLK = 21MHz, fSAMPLE = 500kSPS, and fIN = 10kHz, unless otherwise noted. OUTPUT CODE HISTOGRAM FOR A DC INPUT (8192 Conversions) OUTPUT CODE HISTOGRAM FOR A DC INPUT (8192 Conversions) VA = VBD = 2.7V VREF = 2.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS: AC Performance (continued) At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V, fSCLK = 21MHz, fSAMPLE = 500kSPS, and fIN = 10kHz, unless otherwise noted. SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY 93 95 fIN = 1.03760kHz, -0.2dB 91 90 SNR (dB) SINAD (dB) VA = VBD = 5.0V VREF = 4.096V VA = VBD = 5.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 TYPICAL CHARACTERISTICS: AC Performance (continued) At TA = +25°C, VREF (REF+ – REF–) = 4.096V when VA = VBD = 5V or VREF (REF+ – REF–) = 2.5V when VA = VBD = 2.7V, fSCLK = 21MHz, fSAMPLE = 500kSPS, and fIN = 10kHz, unless otherwise noted. EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY POWER-SUPPLY REJECTION RATIO vs POWER-SUPPLY RIPPLE FREQUENCY 16.0 VA = VBD = 5.0V VREF = 4.096V 15.5 15.0 PSRR (dB) ENOB (Bits) 14.5 14.0 13.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com THEORY OF OPERATION DESCRIPTION The ADS8331/32 is a high-speed, low-power, successive approximation register (SAR) analog-to-digital converter (ADC) that uses an external reference. The architecture is based on charge redistribution, which inherently includes a sample/hold function. The ADS8331/32 has an internal clock that is used to run the conversion.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 Driver Amplifier Choice In order to take advantage of the high sample rate offered by the ADS8331/32, the analog inputs to the converter should be driven with low-noise operational amplifiers (op amps), such as the OPA365, OPA211, OPA827, or THS4031. An RC filter is recommended at each of the input channels to low-pass filter noise generated by the input driving sources.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com REFERENCE The ADS8331/32 can operate with an external reference with a range from 1.2V to 4.2V. A clean, low-noise reference voltage on this pin is required to ensure good converter performance. A low-noise band-gap reference such as the REF5025 or REF5040 can be used to drive this pin. A 10μF ceramic bypass capacitor is required between the REF+ and REF– pins of the converter.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 Auto Channel Select Mode Channel selection can also be done automatically if Auto Channel Select mode (default) is enabled (CFR_D11 = '1'). If the device is programmed for Auto Channel Select mode, then signals from all channels are acquired in a fixed order. In Auto Channel Select mode, the first conversion after entering this mode is always from the channel of the last conversion completed before this mode is enabled.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Start of a Conversion The end of acquisition is the same as the start of a conversion. This process is initiated by bringing the CONVST pin low for a minimum of 40ns. After the minimum requirement has been met, the CONVST pin can be brought high. CONVST acts independently of FS/CS so it is possible to use one common CONVST for applications that require simultaneous sample/hold with multiple converters.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 Power-Down Modes and Acquisition Time There are three power-down modes that reduce power dissipation: Nap, Deep, and Auto-Nap. The first two, Nap and Deep Power-Down modes, are enabled/disabled by bits CFR_D3 and CFR_D2, respectively, in the Configuration register (see Table 5 for details). Deep Power-Down mode provides maximum power savings.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com The ADS8331/32 can support sampling rates of up to 500kSPS in Auto-Trigger mode. This rate is selectable by programming the CFR_D8 bit in the Configuration register. In 500kSPS mode, consecutive conversion start pulses to the analog core are generated 21 conversion clock cycles apart. In 250kSPS mode, consecutive conversion-start pulses are 42 conversion clock cycles apart.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 EOS EOC EOS EOC (active low) Sample (N + 1) Conversion N tH2 Read While Converting CS EOC (N+1) N CONVST Conversion (N + 1) tSU1 Read Result (N - 1) Read While Sampling tSU2 tH1 CS Read Result N Figure 43.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 DIGITAL INTERFACE The serial interface is designed to accommodate the latest high-speed processors with an SCLK frequency of up to 40MHz (VA = VBD = 5.0V). Each cycle starts with the falling edge of FS/CS. The internal data register content, which is made available to the output register at the end of conversion, is presented on the SDO output pin on the falling edge of FS/CS. The first bit is the most significant bit (MSB).
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com WRITING TO THE CONVERTER There are two different types of writes to the register: a 4-bit write to the CMR and a full 16-bit write to the CMR plus CFR. The command set is listed in Table 4 and the configuration register map is listed in Table 5. A simple command requires only four SCLKs; the write takes effect on the fourth falling edge of SCLK.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 READING THE CONVERSION RESULT The conversion result is available to the input of the output data register (ODR) at EOC and presented to the output of the output register at the next falling edge of FS/CS. The host processor can then shift the data out via the SDO pin at any time except during the quiet zone. This duration is 20ns before and 20ns after the end of sampling (EOS) period.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com MICROCONTROLLER INT CS1 CS2 SDI SCLK CONVST CS SDI SCLK CS ADS8331/32 #1 SDO EOC/INT CS3 SDO SCLK CONVST SDI SCLK CS ADS8331/32 #2 CDI Program Device #1: CFR_D5 = ‘1’ SDO SDI CONVST ADS8331/32 #3 CDI SDO Program Devices #2 and #3: CFR_D5 = ‘0’ Figure 46.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 Case 1: If chip select is not toggled (CS stays low), the next 16 bits of data are from the upstream converter, and so on. This configuration is shown in Figure 47. Case 2: If the chip select is toggled during a daisy-chain mode data transfer cycle, as illustrated in Figure 48, the same data from the converter are read out again and again in all three discrete 16-bit cycles. This state is not a desired result.
PAGE 32
ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com Figure 49 shows a slightly different scenario where CONVST is not shared with the second converter. Converters #1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data downstream.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 SCLK skew between converters in a daisy-chain configuration can affect the maximum frequency of SCLK. The skew can also be affected by supply voltage and loading. It may be necessary to slow down the SCLK when the devices are configured in daisy-chain mode. RESET FUNCTION The ADS8331/32 can be reset with three different methods: internal POR, software reset, and external reset using the RESET pin.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com APPLICATION INFORMATION TYPICAL CONFIGURATION EXAMPLE Figure 50 illustrates a typical circuit configuration using the ADS8331/32. Analog +5V 4.7mF AGND External Reference Input 22mF Analog Input AGND VA REF+ REF- AGND MUXOUT ADCIN INX COM Interface Supply +1.8V FS/CS SDO SDI SCLK Host Processor 4.7mF DGND ADS8331/32 CONVST VBD EOC/INT Figure 50.
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ADS8331 ADS8332 www.ti.com SBAS363C – DECEMBER 2009 – REVISED MAY 2012 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8331/32 circuitry. This consideration is particularly true if the reference voltage is low and/or the conversion rate is high. With a conversion clock of 12MHz, the ADS8331/32 makes a bit decision every 83ns.
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ADS8331 ADS8332 SBAS363C – DECEMBER 2009 – REVISED MAY 2012 www.ti.com REVISION HISTORY NOTE: Page numbers from previous revisions may differ from the page numbers in the current version. Changes from Revision B (December 2010) to Revision C Page • Changed name of last column in Low-Power, High-Speed, SAR Converter Family table ...................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 11-Apr-2013 Status (1) ADS8332IRGET ACTIVE Package Type Package Pins Package Drawing Qty VQFN RGE 24 250 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-2-260C-1 YEAR (4) -40 to 85 ADS 8332 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8331IBPWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 ADS8331IBRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 ADS8331IBRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8331IBPWR ADS8331IBRGER TSSOP PW 24 2000 367.0 367.0 38.0 VQFN RGE 24 3000 367.0 367.0 35.0 ADS8331IBRGET VQFN RGE 24 250 210.0 185.0 35.0 ADS8331IPWR TSSOP PW 24 2000 367.0 367.0 38.0 ADS8331IRGER VQFN RGE 24 3000 367.0 367.0 35.0 ADS8331IRGET VQFN RGE 24 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.