Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SSOP 24

Dual, 500kSPS, 16-Bit, 2 + 2 Channel,

Simultaneous Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

● 2 SIMULTANEOUS 16-BIT DACs

● 4 FULLY DIFFERENTIAL INPUT CHANNELS

● 2

μs THROUGHPUT PER CHANNEL

● 4

μs TOTAL THROUGHPUT FOR FOUR CHANNELS

● LOW POWER: 150mW

● INTERNAL REFERENCE

● FLEXIBLE SERIAL INTERFACE

● 16-BIT UPGRADE TO THE 12-BIT ADS7861

● PIN COMPATIBLE WITH THE ADS7861

● OPERATING TEMPERATURE RANGE:

–40

°C to +125°C

APPLICATIONS

● MOTOR CONTROL

● MULTI-AXIS POSITIONING SYSTEMS

● 3-PHASE POWER CONTROL

DESCRIPTION

The ADS8361 is a dual, 16-bit, 500kSPS, Analog-to-Digital

(A/D) converter with four fully differential input channels grouped

into two pairs for high-speed, simultaneous signal acquisition.

Inputs to the sample-and-hold amplifiers are fully differential

and are maintained differentially to the input of the A/D con-

verter. This provides excellent common-mode rejection of

80dB at 50kHz, which is important in high-noise environments.

The ADS8361 offers a high-speed, dual serial interface and

control inputs to minimize software overhead. The output data

for each channel is available as a 16-bit word. The ADS8361

is offered in SSOP-24 and QFN-32 (5x5) packages and is fully

specified over the –40°C to +125°C operating range.

SAR

Serial

Interface

COMP

CLOCK

CONVST

BUSY

SERIAL DATA B

SERIAL DATA A

CDAC

Internal

2.5V

Reference

SHA

CH A0–

CH A0+

REF

CH A1–

CH A1+

SAR

COMP

CDAC

SHA

CH B0–

CH B0+

CH B1–

CH B1+

REF

OUT

ADS8361

SBAS230E – AUGUST 2002 – REVISED AUGUST 2007

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

Summary of content (29 pages)

PAGE 1
ADS ADS8361 836 1 AD S83 61 SBAS230E – AUGUST 2002 – REVISED AUGUST 2007 Dual, 500kSPS, 16-Bit, 2 + 2 Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 2 SIMULTANEOUS 16-BIT DACs ● 4 FULLY DIFFERENTIAL INPUT CHANNELS ● 2μs THROUGHPUT PER CHANNEL ● 4μs TOTAL THROUGHPUT FOR FOUR CHANNELS ● LOW POWER: 150mW ● INTERNAL REFERENCE ● FLEXIBLE SERIAL INTERFACE ● 16-BIT UPGRADE TO THE 12-BIT ADS7861 ● PIN COMPATIBLE WITH THE ADS7861 ● OPERATING TEMPERATURE RANGE: –40°C to +125°
PAGE 2
ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings over operating free-air temperature (unless otherwise noted)(1). This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. Supply Voltage, AGND to AVDD ............................................. –0.3V to 7V Supply Voltage, BGND to BVDD ...............
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ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range at TA = –40°C to +125°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kSPS, unless otherwise noted.
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ELECTRICAL CHARACTERISTICS (Cont.) Over recommended operating free-air temperature range at TA = –40°C to +125°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kSPS, unless otherwise noted. ADS8361 PARAMETER DIGITAL INPUTS(2) Logic Family High-Level Input Voltage Low-Level Input Voltage Input Current Input Capacitance CONDITIONS TYP(1) MAX UNITS VDD + 0.3 0.
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BASIC CIRCUIT CONFIGURATION + ADS8361 + 0.1μF 10μF 10μF 0.1μF +2.7V to +5.5V Digital Supply 1 BGND BVDD 24 2 CH B1+ SERIAL DATA A 23 3 CH B1– SERIAL DATA B 22 4 CH B0+ BUSY 21 5 CH B0– CLOCK 20 Clock Input 6 CH A1+ CS 19 Chip Select 7 CH A1– RD 18 Read Input 8 CH A0+ CONVST 17 9 CH A0– A0 16 A0 Address Select 10 REFIN M0 15 M0 Address Select 11 REFOUT M1 14 M1 Address Select 12 AGND AVDD 13 BUSY Output Conversion Start + +5V Analog Supply 10μF 0.
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PIN CONFIGURATION NC(2) NC(2) NC(2) BGND BVDD NC(2) SERIAL DATA A 30 29 28 27 26 25 QFN NC(2) Top View 31 SSOP 32 Top View ADS8361 1 BGND 2 CH B1+ SERIAL DATA A 23 3 CH B1– SERIAL DATA B 22 CH B1+ 1 24 SERIAL DATA B 4 CH B0+ BUSY 21 CH B1− 2 23 BUSY 5 CH B0– CLOCK 20 CH B0+ 3 22 CLOCK CH B0− 4 21 CS CH A1+ 5 20 RD CH A1− 6 19 CONVST CH A0+ 7 18 A0 CH A0− 8 17 M0 12 AGND 16 M1 M1 14 15 11 REFOUT NC(2) M0 15 14 10 REFIN NC(2) A0 16 C
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TIMING CHARACTERISTICS tCKH CLOCK 1 0 2 3 4 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 tCKL t6 t1 CONVST t11 t2 t3 A0 t4 t5 t7 RD t8 CS t9 t8 t10 Serial Data A CH 0/1 CH A/B D15 D14 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D15 D14 D13 D12 Serial Data B CH 0/1 0 D15 D14 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D15 D14 D13 D12 BUSY tCONV tACQ tCONV TIMING CHARACTERISTICS Timing Characteristics over recommended operating free-air temperatu
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TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kSPS, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE INTEGRAL LINEARITY ERROR vs CODE 5 3 Typical curve for all four channels.
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TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 10MHz, and fSAMPLE = 500kSPS, unless otherwise noted. FREQUENCY SPECTRUM (4096 point FFT, fIN = 5kHz, –0.
PAGE 10
INTRODUCTION REFERENCE The ADS8361 is a high-speed, low-power, dual, 16-bit A/D converter that operates from +3V/+5V supply. The input channels are fully differential with a typical common-mode rejection of 80dB. The part contains dual, 4μs successive approximation A/D converter, two differential sample-andhold amplifiers, an internal +2.5V reference with REFIN and REFOUT pins, and a high-speed serial interface. The ADS8361 requires an external clock.
PAGE 11
+IN CM + VREF +VREF CM Voltage –IN = CM Voltage –VREF t CM – VREF CM + 1/2 VREF Single-Ended Inputs +IN +VREF CM Voltage CM – 1/2 VREF –VREF –IN t Differential Inputs NOTES: Common-Mode Voltage (Differential Mode) = (+IN) + (–IN) , Common-Mode Voltage (Single-Ended Mode) = IN–. 2 The maximum differential voltage between +IN and –IN of the ADS8361 is VREF. See Figures 3 and 4 for a further explanation of the common voltage range for single-ended and differential inputs. FIGURE 2.
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TRANSITION NOISE BIPOLAR INPUTS The transition noise of the ADS8361 itself is low, as shown in Figure 5. These histograms were generated by applying a low-noise DC input and initiating 8000 conversions. The digital output of the A/D converter will vary in output code due to the internal noise of the ADS8361. This is true for all 16bit, Successive Approximation Register (SAR-type) A/D converters.
PAGE 13
0111 1111 1111 1111 65535 0111 1111 1111 1110 65534 0111 1111 1111 1101 65533 0000 0000 0000 0001 32769 0000 0000 0000 0000 32768 1111 1111 1111 1111 32767 1000 0000 0000 0010 Step Digital Output Code Binary Two’s Complement BTC 2 1000 0000 0000 0001 1 1000 0000 0000 0000 0 2.499962V VNFS = VCM – VREF = 0V 0.000038V 2.500038V VPFS = VCM + VREF = 5V VPFS – 1LSB = 4.999924V VBPZ = 2.5V 0.000076V 4.999848V Unipolar Analog Input Voltage 0.
PAGE 14
Mode II (M0 = 0, M1 = 1) With M1 set to ‘1’, the ADS8361 will output data on the Serial Data A pin only. All other pins function in the same manner as Mode I except that the Serial Data B output will tri-state (i.e., high impedance) after a conversion following M1 going HIGH. Another difference in this mode involves the CONVST pin.
PAGE 15
1 20 CLOCK Conversion of Ch0 Conversion of Ch1 CONVST A0 LOW, Next Conversion: Ch0 A0 HIGH, Next Conversion: Ch1 A0 RD Connected to CONVST RD CS CS HIGH, Outputs in Tri-State Serial Data A 16-Bit Data of Chx 16-Bit Data of ChA1 Serial Data B 16-Bit Data of Chx 16-Bit Data of ChB1 Conversion of Chx BUSY TIME 0 Conversion of Ch0 Conversion of Ch1 1μ 2μ 3μ 4μ 5μ 6μ Time (seconds) FIGURE 10. Mode I, Timing Diagram for M0 = 0 and M1 = 0.
PAGE 16
1 20 CLOCK 4-Ch Operation and 1st Conversion Ch0 CONVST M0 = 1 A0 Ignored A0 M0 RD 4-Ch Operation and 2nd Conversion Ch1 M0 = 1, 4-Ch Operation Starts with Next Conversion RD Connected with CONVST CS CS LOW, Output is Active Serial Data A 16-Bit Data of ChAx C h 0 16-Bit Data of ChA0 C h 1 16-Bit Data of ChA1 Serial Data B 16-Bit Data of ChBx C h 0 16-Bit Data of ChB0 C h 1 16-Bit Data of ChB1 BUSY TIME 0 1μ 2μ 3μ 4μ 5μ 6μ Time (seconds) FIGURE 12.
PAGE 17
1 20 CLOCK M1 = 1 and 1st CONVST Conversion Conversion of Chx CONVST M1 = 1 and 2nd CONVST No Conversion M1 = 1 and 1st CONVST Conversion M1 = 1 and 2nd CONVST No Conversion M0 HIGH 4-Ch Operation Starts, A0 Ignored A0 M0 M0 HIGH 4-Ch Operation Starts M1 M1 HIGH Only Serial Data A Used as Output Starting with 1st Conversion RD M0 = 1 and 1st Active CONVST Ch0 M0 = 1 and 2nd Active CONVST Ch1 RD Connected with CONVST CS LOW Output Active CS Serial Data A Serial Data B BUSY CC hh 0A 16
PAGE 18
TMS320F28xx/ C54xx/C67xx ADS8361 DR SERIAL DATA A CONVST FSX RD FSR CLOCK CLKX CLKR BVDD EXT_INT BUSY M1 A0 M0 CS DX FIGURE 15. 2x2 Channel Using A Output. TMS320C54xx/ C67xx ADS8361 SERIAL DATA A DRA SERIAL DATA B DRB CONVST FSXA RD FSRA FSRB CLOCK BVDD M1 CLKXA CLKRA CLKRB M0 CS FIGURE 16. 4-Channel Sequential Mode Using A and B Outputs. TMS320F28xx/ C54xx/C67xx ADS8361 SERIAL DATA A DRX CONVST FSX RD FSR CLOCK BVDD M0 CLKX CLKR M1 CS FIGURE 17.
PAGE 19
Revision History DATE REVISION PAGE SECTION E Pin Configuration Added Note (1) to QFN package. Entire Document Changed Throughput Rate from 500kHz to 500kSPS throughout document. 8/07 6 1 Features Description 2 8/06 Absolute Maximum Ratings Package/Ordering Table D DESCRIPTION Added Operating Temperature Range: –40°C to +125°C. Changed Operating Temperature Range upper limit from +85°C to +125°C. Changed Operating Temperature Range upper limit from +85°C to +125°C. Deleted Lead Temperture.
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.
PAGE 21
PACKAGE OPTION ADDENDUM www.ti.com (4) 27-Jul-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 3-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8361IDBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 ADS8361IRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 ADS8361IRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
PAGE 23
PACKAGE MATERIALS INFORMATION www.ti.com 3-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8361IDBQR SSOP DBQ 24 2500 367.0 367.0 38.0 ADS8361IRHBR VQFN RHB 32 3000 367.0 367.0 35.0 ADS8361IRHBT VQFN RHB 32 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.