ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 Dual, 1MSPS, 16-/14-/12-Bit, 4×2 or 2×2 Channel, Simultaneous Sampling Analog-to-Digital Converter Check for Samples: ADS8363, ADS7263, ADS7223 FEATURES DESCRIPTION • • • The ADS8363 is a dual, 16-bit, 1MSPS analog-to-digital converter (ADC) with eight pseudoor four fully-differential input channels grouped into two pairs for simultaneous signal acquisition.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS: ADS8363 All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA = 1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS7223 All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA = 1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V. ADS7223 PARAMETER TEST CONDITIONS MIN RESOLUTION TYP MAX 12 UNIT Bits DC ACCURACY INL Integral nonlinearity –0.5 ±0.2 +0.5 LSB DNL Differential nonlinearity –0.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 ELECTRICAL CHARACTERISTICS: GENERAL (continued) All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA = 1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL (continued) All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA = 1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V. ADS8363, ADS7263, ADS7223 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVDD to AGND, half-clock mode 2.7 5.0 5.5 V AVDD to AGND, full-clock mode 4.5 5.
ADS8363 ADS7263 ADS7223 www.ti.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com Pin Descriptions (continued) PIN 8 NAME NO. TYPE (1) CS 21 DI Chip select. When this pin is low, the SDOx, SDI, and RD pins are active; when this pin is high, the SDOx outputs are 3-stated, while the SDI and RD inputs are ignored. CLOCK 22 DI External clock input. The range is 0.5MHz to 20MHz in half-clock mode, or 1MHz to 40MHz in full-clock mode. BUSY 23 DO Converter busy indicator.
ADS8363 ADS7263 ADS7223 www.ti.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 TIMING CHARACTERISTICS (1) Over the recommended operating free-air temperature range of –40°C to +125°C, and DVDD = 2.3V to 5.5V, unless otherwise noted. ADS8363, 7263, 7223 PARAMETER tDATA Data throughput tCONV Conversion time tACQ Acquisition time fCLK TEST CONDITIONS fCLK = max MIN MAX 1 ms Half-clock mode 17.5 tCLK Full-clock mode 35 tCLK 100 Half-clock mode CLOCK frequency UNIT 0.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = 5V, DVDD = 3.3V, VREF = 2.5V (internal), and fDATA = 1MSPS, unless otherwise noted. INTEGRAL NONLINEARITY vs DATA RATE DIFFERENTIAL NONLINEARITY vs DATA RATE 3.0 3.0 ADS8363 Positive ADS7263 Positive ADS7223 Positive 2.5 2.0 1.5 1.5 1.0 1.0 0.5 0 -0.5 -1.0 -1.5 200 300 400 500 600 700 Data Rate (kSPS) 800 900 0 -0.5 -1.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, DVDD = 3.3V, VREF = 2.5V (internal), and fDATA = 1MSPS, unless otherwise noted. OFFSET ERROR AND OFFSET MATCH vs ANALOG SUPPLY VOLTAGE OFFSET ERROR AND OFFSET MATCH vs TEMPERATURE 2.0 2.0 All Devices Offset Error Offset Match 1.5 Offset Error and Match (mV) Offset Error and Match (mV) All Devices 1.0 0.5 0 -0.5 -1.0 0.5 0 -0.5 -1.0 -2.0 -2.0 2.7 3.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, DVDD = 3.3V, VREF = 2.5V (internal), and fDATA = 1MSPS, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 10kHz) FREQUENCY SPECTRUM (4096 Point FFT; fIN = 10kHz, fSAMPLE = 0.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = 5V, DVDD = 3.3V, VREF = 2.5V (internal), and fDATA = 1MSPS, unless otherwise noted.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com THEORY OF OPERATION GENERAL DESCRIPTION The ADS8363/7263/7223 contain two 16-/14-/12-bit analog-to-digital converters (ADCs), respectively, that operate based on the successive approximation register (SAR) principle. These ADCs sample and convert simultaneously. Conversion time can be as low as 875ns.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 Acquisition is indicated with the BUSY signal being low. It starts by closing the input switches (after finishing the previous conversion and precharging) and finishes with the rising edge of the CONVST signal. If the device operates at full speed, the acquisition time is typically 100ns.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com signal should be continuously running. However, in applications that use the device in burst mode, the clock may be held static low or high upon completion of the read access and before starting a new conversion. capacitor connected. Smaller reference capacitance values reduce the DNL, INL, and ac performance of the device. By default, both reference outputs are disabled and the respective values are set to 2.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 DIGITAL This section reviews the timing and control of the serial interface. The ADS8363/7263/7223 offer a set of internal registers (see the Register Map section for details), which allows the control of several features and modes of the device, as Table 5 shows. Mode Selection Pin M0 and M1 The ADS8363/7263/7223 can be configured to four different operating modes by using mode pins M0 and M1, as shown in Table 4. Table 4.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com REGISTERS Register Map ADS8363/7263/7223 operation is controlled through a set of registers described in the following sections. Table 6 shows the register map. The contents of these 16-bit registers can be set using the serial data input (SDI) pin, which is coupled to RD and clocked into the device on each falling edge of CLOCK. All data must be transferred MSB first.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 Configuration (CONFIG) Register The configuration register selects the input channel, the activation of power-down modes, and the access to the sequencer/FIFO, reference selection, and reference DAC registers. Table 7.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 Bits[3:0] www.ti.com A[3:0]—Register access control. These bits allow reading of the CONFIG register contents and control the access to the remaining registers of the device. x000 = Update CONFIG register contents only (default) 0001 = Read CONFIG register content on SDOA with next access (see Figure 30). x010 = Write to REFDAC1 register with next access (see Figure 30).
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 REFDAC1 and REFDAC2 Registers Two reference DAC registers allow for enabling and setting up the appropriate value for each of the output string DACs that are connected to the REFIO1 and REFIO2 pins. Table 8. REFDAC1 Control Register (default = 07FFh) MSB BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 0 0 0 0 0 RPD Bits[15:11] Not used; always set to '0'. Bit 10 RPD—DAC1 power down.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com Sequencer/FIFO (SEQFIFO) Register The ADS8363/7363/7223 feature a programmable sequencer that controls the switching of the ADC input multiplexer in pseudo-differential, automatic channel-selection mode only. When used, a single read pulse allows reading of all stored conversion data. A single CONVST is required to control the conversion of the entire sequence.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 Bits[3:2] SP[1:0]—Sequence position bits (read only). These bits indicate the setting of the pseudo-differential input multiplexer in sequencer mode.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com FD[1:0] = ‘01’, SL[1:0] = ‘00’ … CONVST BUSY Conversion 1 … Conversion 2 … RD … CONV1 CONV2 SDOx (2x16 clock cycles) FD[1:0] = ‘01’, SL[1:0] = ‘10’ … CONVST BUSY 1.CHx2 1.CHx1 1.CHx0 2.CHx2 2.CHx1 2.CHx0 CHx1+ … … RD 1.CHx2 1.CHx1 1.CHx0 2.CHx2 2.CHx1 2.CHx0 SDOx … (6x16 clock cycles) Figure 33.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 Reference and Common-Mode Selection (REFCM) Register To allow flexible adjustment of the common-mode voltage in pseudo-differential mode while simplifying the circuit layout, the ADS8363/7263/7223 provide this register to assign one of the CMx inputs as a reference for each of the input signals. According to the register settings, the CMx signals are internally connected to the appropriate negative input of each ADC.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com READ DATA INPUT (RD) The RD input is used to control serial data outputs SDOx. The falling edge of the RD pulse triggers the output of the first bit of the output data.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 Mode I With the M0 and M1 pins both set to '0', the device enters manual channel-control operation and outputs data on both SDOA and SDOB, accordingly. The SDI pin can be used to switch between the channels, as explicitly shown in the corresponding timing diagrams. A conversion is initiated by bringing CONVST high.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com Mode II (Half-Clock Mode Only) With M0 = '0' and M1 = '1', the ADS8363/7263/7223 also operate in manual channel-control mode and output data on the SDOA pin only while SDOB is set to high impedance. All other pins function in the same manner as they do in Mode I. In half-clock mode, because it takes 40 clock cycles to output the results from both ADCs (instead of 20 cycles if M1 = '0'), the device requires 2.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 Special Read Mode II (Half-Clock Mode Only) For Mode II, a special read mode is available in the ADS8363/7263/7223 where both data results can be read out triggered by a single RD pulse (refer to Figure 36). To activate this mode, The SR bit in the CONFIG register must be set to '1' (see Table 6). The CONVST and RD pins can still be tied together but are issued every 40 CLOCK cycles instead of 20.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com Mode III This mode can be used for fullyor pseudo-differential inputs (in pseudo-differential mode the sequencer is used to control the input multiplexer). Channel information is available in fully-differential mode only if CID = '0' (CID is forced to '1' in pseudo-differential mode).
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 Fully-Differential Mode IV (Half-Clock Mode Only) In the same way as Mode II, Mode IV uses the SDOA output line exclusively to transmit data while the differential channels are switched automatically. Following the first conversion after M1 goes high, the SDOB output 3-states, as shown in Figure 38.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com Special Mode IV (Half-Clock Mode Only) If auto-sleep power-down mode is enabled, the conversion results are presented during the next conversion, as shown in Figure 39. As with Special Mode II, these devices also offer a special read mode for Mode IV, where both data results of a conversion can be read by triggering a single RD pulse (refer to Figure 39).
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 PROGRAMMING THE REFERENCE DAC When channel information is enabled (CID = '0'), the first two bits of the data output contain the currently selected analog input channel indicator ('0' for CHx0 or '1' for CHx1), followed by the 16-bit DAC register contents and an additional '00'.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com POWER-DOWN MODES AND RESET These devices have a comprehensive built-in power-down feature. There are three power-down modes: Power-Down, Sleep, and Auto-Sleep Power-Down. All three power-down modes are activated with the completion of the write access, during which the related bit(s) are asserted (PD[1:0]). All modes are deactivated by deasserting the respective bit(s) in the CONFIG register.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 Half-Clock Mode CLOCK CONVST tACQ BUSY Auto-Sleep Power-Down conversion n 7 CLOCKs conversion n + 1 Full-Clock Mode CLOCK CONVST tACQ BUSY Auto-Sleep Power-Down conversion n 14 CLOCKs conversion n + 1 Figure 41.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com SDI versus A0 • Pin 18 (SDI) of the ADS8363/7263/7223 is used to update the internal registers, whereas on the ADS8361, pin 18 (A0) is used in conjunction with M0 to select the input channel.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 APPLICATION INFORMATION MINIMUM CONFIGURATION EXAMPLE Those values can be calculated using Equation 5: ln(2)(n + 1) fFILTER = 2p2RC An example of a minimum configuration for the ADS8363/7263/7223 is shown in Figure 42. In this case, the device is used in dual-channel, fully-differential input mode with a four-wire digital interface connected to the controller device and with default settings of the device after power up.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8363/7263/7223 circuitry, particularly if the device is used at the maximum throughput rate. In this case, it is recommended to have a fixed phase relationship between CLOCK and CONVST.
ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com to AVDD to DVDD 25 26 DGND 1 mF AVDD 31 AGND 32 1 mF DVDD (Top View) 19 7 18 8 17 22mF 16 6 15 20 14 21 5 AVDD 22 4 AGND 23 3 RGND 2 REFIO2 24 REFIO1 1 1mF LEGEND 22mF Top layer: copper pour and traces Lower layer: AGND area to AVDD Lower layer: DGND area via Figure 44.
ADS8363 ADS7263 ADS7223 www.ti.com SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December, 2010) to Revision B Page • Revised test conditions for gain error parameter .................................................................................................................. 3 • Revised test conditions for gain error parameter ................................
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