Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal VQFN 28 EP

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FEATURES APPLICATIONS

DESCRIPTION

CDAC

Output

Latches

and

3-State

Drivers

SAR

Conversion

and

Control Logic

Comparator

Clock

+IN

−IN

REFIN

CONVST

BUSY

4.096-V

Internal

Reference

REFOUT

SCLK

SDO

SB/2C

ADS8380

SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004

18-BIT, 600-kHz, PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING

ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE AND REFERENCE

• 600-kHz Sample Rate • Medical Instruments

• Optical Networking

• ±2 LSB Typ, ±4 LSB Max INL

• Transducer Interface

• 18-Bit NMC Ensured Over Temperature

• High Accuracy Data Acquisition Systems

• SINAD 91 dB, SFDR 119 dB at f

= 1 kHz

• Magnetometers

• High-Speed Serial Interface up to 40 MHz

• Onboard Reference Buffer

• Onboard 4.096-V Reference

The ADS8380 is a high performance 18-bit, 600-kHz

• Pseudo-Differential Input, 0 V to 4.2 V

A/D converter with single-ended (pseudo-differential)

• Onboard Conversion Clock

input. The device includes an 18-bit capacitor-based

• Selectable Output Format, 2's Complement or

SAR A/D converter with inherent sample and hold.

Straight Binary

The ADS8380 offers a high-speed CMOS serial

• Zero Latency

interface with clock speeds up to 40 MHz.

• Wide Digital Supply

The ADS8380 is available in a 28 lead 6 × 6 QFN

• Low Power:

package and is characterized over the industrial

–40°C to 85°C temperature range.

– 115 mW at 600 kHz

– 15 mW During Nap Mode

– 10 µ W During Power Down

• 28-Pin 6 x 6 QFN Package

High Speed SAR Converter Family

Type/Speed 500 kHz ~ 600 kHz 750 kHZ 1 MHz 1.25 MHz 2 MHz 3 MHz 4 MHz

ADS8383 ADS8381

18-Bit Pseudo-Diff

ADS8380 (S)

18-Bit Pseudo-Bipolar, Fully Diff ADS8382 (S)

16-Bit Pseudo-Diff ADS8371 ADS8401/05 ADS8411

16-Bit Pseudo-Bipolar, Fully Diff ADS8402/06 ADS8412

14-Bit Pseudo-Diff ADS7890 (S) ADS7891

12-Bit Pseudo-Diff ADS7886 ADS7881

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

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ADS8380 SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 18-BIT, 600-kHz, PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE AND REFERENCE FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • 600-kHz Sample Rate ±2 LSB Typ, ±4 LSB Max INL 18-Bit NMC Ensured Over Temperature SINAD 91 dB, SFDR 119 dB at fi = 1 kHz High-Speed Serial Interface up to 40 MHz Onboard Reference Buffer Onboard 4.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) MODEL MAXIMUM INTEGRAL LINEARITY (LSB) ADS8380I ADS8380IB (1) MAXIMUM DIFFERENTIAL LINEARITY (LSB) ±6 NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE 17 28 Pin 6×6 QFN –2/2.5 ±4 –1/1.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 SPECIFICATIONS At –40°C to 85°C, +VA = +5 V, +VBD = +5 V or +VBD = +2.7 V, using internal or external reference, fSAMPLE = 600 kHz, unless otherwise noted. (All performance parameters are valid only after device has properly resumed from power down, see Table 2.) PARAMETER TEST CONDITIONS ADS8380IB MIN ADS8380I TYP MAX MIN TYP MAX 0 Vref 0 Vref +IN –0.2 Vref + 0.2 -0.2 Vref + 0.2 –IN –0.2 0.2 -0.2 0.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 SPECIFICATIONS (continued) At –40°C to 85°C, +VA = +5 V, +VBD = +5 V or +VBD = +2.7 V, using internal or external reference, fSAMPLE = 600 kHz, unless otherwise noted. (All performance parameters are valid only after device has properly resumed from power down, see Table 2.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 TIMING REQUIREMENTS (1) (2) (3) (4) (5) (6) ADS8380I/ADS8380IB PARAMETER MIN TYP MAX UNIT REF FIGURE tconv Conversion time 1000 1160 ns 41 – 44 tacq1 Acquisition time in normal mode 0.5 1000 µs 41,42,44 tacq2 Acquisition time in nap mode (tacq2 = tacq1 + td18) 0.
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ADS8380 www.ti.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 PIN ASSIGNMENTS 28 27 26 25 24 23 22 PD FS CS CONVST SCLK SDO BUSY TOP VIEW 1 SB/2C BDGND 21 2 AGND +VBD 20 3 +VA AGND 19 4 AGND AGND 18 5 AGND +VA 17 6 +VA +VA 16 7 REFM AGND 15 +VA −IN 12 14 +IN 11 NC NC 10 13 REFOUT 9 8 REFIN ADS8380 TERMINAL FUNCTIONS PIN NAME AGND NO. I/O DESCRIPTION 2, 4, 5, 15, 18, 19 – Analog ground pins.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE AND DISTORTION vs REFERENCE VOLTAGE SNR − Signal-to-Noise Ratio − dB 92 fi = 1 kHz, +VA = 5 V, +VBD = 5 V, TA = 25°C 91 90 89 88 87 86 85 3 3.5 Vref − Reference Voltage − V 4 92 90 89 88 87 86 85 2.5 4 SPURIOUS FREE DYNAMIC RANGE vs REFERENCE VOLTAGE TOTAL HARMONIC DISTORTION vs REFERENCE VOLTAGE −112 120 fi = 1 kHz, +VA = 5 V, +VBD = 5 V, TA = 25°C 119.5 119 118.5 118 117.5 117 116.5 3.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE AND DISTORTION vs FREE-AIR TEMPERATURE SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE 91.8 91.6 91.4 91.2 91 90.8 90.6 −40 −25 −10 SFDR − Spurious Free Dynamic Range − dB SINAD − Signal-To-Noise and Distortion − dB fi = 1 kHz +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V 5 20 35 50 65 92 91.6 91.4 91.2 91 90.8 90.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE RATIO vs INPUT FREQUENCY SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY SNR − Signal-to-Noise Ratio − dB 91.5 91 90.5 90 89.5 89 +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V TA = 25°C 88.5 88 10 1 140 SFDR − Spurious Free Dynamic Range − dB 92 120 100 80 60 40 +VA = 5 V, +VBD = 5 V, REFIN = 4.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) GAIN ERROR vs REFERENCE VOLTAGE GAIN ERROR vs SUPPLY VOLTAGE 0.5 1.6 +VA = 5 V, +VBD = 5 V, TA = 25°C 0.45 1.2 0.35 0.3 0.25 0.2 0.15 0.1 1 0.8 0.6 0.4 0.2 0 −0.2 0.05 0 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 Vref − Reference Voltage − V −0.4 4.75 4.1 5 +VA − Supply Voltage − V Figure 18. Figure 19. GAIN ERROR vs FREE-AIR TEMPERATURE OFFSET ERROR vs REFERENCE VOLTAGE 5.25 0.5 0.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) POWER DISSIPATION vs SUPPLY VOLTAGE POWER DISSIPATION vs SAMPLE RATE 140 116 PD − Power Dissipation − mW 114 112 PD − Power Dissipation − mW +VBD = 5 V, fs = 600 KSPS TA = 25°C 110 108 106 104 102 Normal Mode Current 100 80 60 NAP Mode Current 40 +VA = 5 .25 V, +VBD = 5.25 V, TA = 25°C 20 0 100 4.75 5 +VA − Analog Supply Voltage − V 0 5.25 300 400 500 600 Figure 25.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) 4 3.5 +VA = 5 V, +VBD = 5 V, 3 REFIN = 4.096 V 2.5 2 1.5 1 0.5 0 −0.5 −1 Min −1.5 −2 −2.5 −3 −3.5 −4 −40 −25 −10 5 20 INTERNAL VOLTAGE REFERENCE vs FREE-AIR TEMPERATURE 4.126 Internal Reference Output Voltage − V INL − Integral Nonlinearity − LSBs INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE Max +VA = 5 V, +VBD = 5 V, 4.116 4.106 4.096 4.086 4.076 4.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) INTEGRAL NONLINEARITY 2 1.5 1 INL − LSBs 0.5 0 −0.5 −1 +VA = 5 V, +VBD = 5 V, fs = 600 KSPS, REFIN = 4.096 V, TA = 25°C −1.5 −2 −2.5 0 32768 65536 98304 131072 163840 196608 229376 262144 Straight Binary Code in Decimal Figure 35. FFT (100 kHz Input) 0 −20 +VA = 5 V, +VBD = 5 V, fs = 600 KSPS, fi = 100 kHz, REFIN = 4.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 Power On BUSY=0 +VA and +VBD Reach Operation Range and PD = 0 Sample BUSY=0 CS = 0 and CONVST = 1 Falling Edge of CONVST_QUAL SOC BUSY=0 −> 1 CS = 0 and CONVST = 1 Back to Back Cycle CS = 0 and CONVST = 1 Falling Edge of CONVST_QUAL and BUSY = 1 CONVERSION Abort EOC BUSY= 1−>0 CONVST_QUAL = 0 A.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 CONVST_QUAL tquiet1 tquiet2 BUSY tquiet3 CS Quiet Zones FS tsu3 CS th8 tsu2 BUSY th2 No Read Zone (FS Initiated) BUSY No Read Zone (CS Initiated) Figure 40. Quiet Zones and No-Read Zones CONVERSION AND SAMPLING 1. Convert start command: The device enters the conversion phase from the sampling phase when a falling edge is detected on CONVST_QUAL. This is shown in Figure 41, Figure 42, and Figure 43. 2.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 3. Wait/Nap entry stimulus: The device enters the wait phase at the end of the conversion if the sample start command is not given. This is shown in Figure 42. tw2 tsu4 CS th4 CONVST CONVST_QUAL (Device Internal) tquiet2 tquiet2 tquiet1 tquiet1 DEVICE STATE SAMPLE CONVERT SAMPLE WAIT tCONV tacq1 td2 BUSY tquiet3 Figure 42.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 4. Conversion abort command An ongoing conversion can be aborted by using the conversion abort command. This is done by forcing another start of conversion (a valid CONVST_QUAL falling edge) onto an ongoing conversion as shown in Figure 44. The device enters the wait state after an aborted conversion. If the previous conversion was successfully aborted, the device output reads 0x3FC00 on SDO.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 2 1 SCLK 3 4 16 tsu5 th5 17 18 19 tcyc td14 CS tw2 tquiet2 CONVST tquiet1 td13 SDO MSB D17 BUSY LSB D16 D15 D14 D3 D2 D1 D17 Repeated If There is 19th SCLK td12 tquiet3 D0 Conversion N Conversion N+1 th2 tsu2 CS Fall Before This Point Reads Data From Conversion N−1 CS Fall After This Point Reads Data From Conversion N No CS Fall Zone Figure 45.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 1 SCLK 2 4 16 17 18 19 tcyc th6 tsu7 CS tsu6 3 tw3 FS CONVST MSB of Conversion N−1 MSB of Conversion N td15 SDO D17 D16 D15 tquiet1 td13 D14 D3 D2 D1 LSB D0 tquiet2 D17 Repeated If There is 19th SCLK td7 tquiet3 BUSY Conversion N+1 Conversion N th8 tsu3 FS Fall Before This Point Reads Data From Conversion N−1 No FS Fall Zone FS Fall After This Point Reads Data From Conversion N Figure 47.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 PRINCIPLES OF OPERATION (continued) ADS8380 REFOUT REFIN 1 mF 0.1 mF REFM AGND Figure 48. ADS8380 Using Internal Reference The REFIN pin is also internally buffered. This eliminates the need to put a high bandwidth buffer on the board to drive the ADC reference and saves system area and power.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 PRINCIPLES OF OPERATION (continued) signals. Essentially, the current into the ADS8380 charges the internal capacitor array during the sampling (acquisition) time. After this capacitance has been fully charged, there is no further input current.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 DIGITAL INTERFACE (continued) READING DATA The ADS8380 offers a high speed serial interface that is compatible with the SPI protocol. The device outputs data in either 2's complement format or straight binary format depending on the state of the SB/2C pin. Refer to Table 1 for the ideal output codes. Table 1.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 PD ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ tw4 td10 Valid Data Invalid Data SDO td11 1 td18 2 3 BUSY REFOUT ICC td17 td16 Full ICC ICC PD Full ICC Figure 53. Device Full Power Down/Resume (Internal Refernce Used) PD tw4 td10 SDO ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ Invalid Data td11 td18 1 2 Valid Data 3 BUSY tacq1 td16 ICC Full ICC ICC PD Full ICC Figure 54.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 PD = 0 CONVST CS CONVST_QUAL DEVICE STATE SAMPLE CONVERT NAP SAMPLE Hi−Z SDO LSB+1 LSB MSB MSB−1 tCONV BUSY REFIN (or REFOUT) td18 td16 ICC Full ICC ICC NAP Full ICC Figure 55. Device Nap Power Down/Resume LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8380 circuitry.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 Table 3. Power Supply Decoupling Capacitor Placement SUPPLY PINS Pair of pins requiring a shortest path to decoupling capacitors CONVERTER ANALOG SIDE CONVERTER DIGITAL SIDE (2,3); (5,6); (15,16); (17,18) (20,21) Pins requiring no decoupling 4, 14, 19 When using the internal reference, ensure a shortest path from REFOUT (pin 9) to REFIN (pin 8) with the bypass capacitor directly between pins 8 and 7.
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ADS8380 www.ti.com SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004 APPLICATION INFORMATION (continued) It is also possible to use the frame sync signal, FS. The following timing diagram shows how to achieve a 600-KSPS throughput using a modified serial interface with FS active. BUSY DEVICE STATE CONVERT SAMPLE CONVERT 485 ns Frequency = 600 kHz CONVST 50 ns CS = 0 15 ns 15 ns 30ns FS 25 ns 1 2 3 17 18 SCLK 12.5 ns SDO LSBn−1 D0 MSBn D17 LSBn D16 D15 D2 D1 D0 Figure 57.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8380IBRHPT VQFN RHP 28 250 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 ADS8380IRHPT VQFN RHP 28 250 330.0 16.4 6.3 6.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8380IBRHPT VQFN RHP 28 250 336.6 336.6 28.6 ADS8380IRHPT VQFN RHP 28 250 336.6 336.6 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.