Datasheet

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SOC
BUSY=0 −> 1
Wait
BUSY=0
Sample
BUSY=0
NAP
BUSY=0
EOC
BUSY= 1−>0
Power
On
BUSY=0
CS = 0 and CONVST = 1
CS = 0 and CONVST = 1
Back to Back Cycle
CS = 0 and CONVST = 1
Falling Edge of
CONVST_QUAL
and BUSY = 1
Abort
CONVST_QUAL = 0
CONVST_QUAL = 1
and CS = 1
Falling Edge of CONVST_QUAL
CONVERSION
+VA and +VBD Reach Operation Range
and PD = 0
D
Q
LATCH
LATCH
CONVST
CS
CONVST_QUAL
TIMING DIAGRAMS
ADS8380
SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004
A. EOC = End of conversion, SOC = Start of conversion, CONVST_QUAL is CONVST latched by CS = 0, see
Figure 39 .
Figure 38. Device States and Ideal Transitions
Figure 39. Relationship Between CONVST_QUAL, CS, and CONVST
In the following descriptions, the signal CONVST_QUAL represents CONVST latched by a low value on CS (see
Figure 39 ).
To avoid performance degradation, there are three quiet zones to be observed (t
quiet1
and t
quiet2
are zones before
and after the falling edge of CONVST_QUAL while t
quiet3
is a time zone before the falling edge of BUSY) where
there should be no I/O activities. Interface control signals, including the serial clock should remain steady.
Typical degradation in performance if these quiet zones are not observed is depicted in the specifications
section.
To avoid data loss a read operation should not start around the BUSY falling edge. This is constrained by t
su2
,
t
su3
, t
h2
, and t
h8
.
15
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