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t
quiet2
t
quiet1
t
quiet2
t
quiet1
CS
CONVST
CONVST_QUAL
(Device Internal)
DEVICE STATE
BUSY
t
w2
t
h4
t
su4
CS
t
d2
SAMPLE CONVERT SAMPLE
t
CONV
t
acq1
t
quiet3
WAIT
CS
CONVST
CONVST_QUAL
DEVICE STATE
BUSY
NAP
t
h3
t
d5
t
w1
t
d3
t
d1
t
quiet2
t
quiet1
t
quiet2
t
quiet1
t
d4
SAMPLE CONVERT
t
CONV
t
acq2
t
quiet3
t
quiet3
NAP SAMPLE CONVERT NAP SAMPLE
t
d2
(Device Internal)
ADS8380
SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004
3. Wait/Nap entry stimulus:
The device enters the wait phase at the end of the conversion if the sample start command is not given.
This is shown in Figure 42 .
Figure 42. Convert and Sample with Wait
If lower power dissipation is desired and throughput can be compromised, a nap state can be inserted in
between cycles (as shown in Figure 43 ). The device enters a low power (3 mA) state called nap if the end of
the conversion happens when CONVST_QUAL is low. The cost for using this special wait state is a longer
sampling time (t
acq2
) plus the nap time.
Figure 43. Convert and Sample with Nap
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