Datasheet

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CS
CONVST
SDO
D17
1 16 17 18 19
SCLK
LSB
BUSY
D2D16 D15
Conversion N+1
D14 D3 D1 D0
t
h6
t
su7
t
cyc
t
su6
t
w3
t
d15
MSB of Conversion N−1
MSB of Conversion N
t
d13
t
d7
t
h8
t
su3
D17 Repeated
No FS
Fall
Zone
FS Fall After This
Point Reads Data
From Conversion
N
FS Fall Before This
Point Reads Data
From Conversion
N−1
If There is 19th SCLK
Conversion N
t
quiet2
t
quiet1
FS
t
quiet3
2 3 4
PRINCIPLES OF OPERATION
REFERENCE
ADS8380
SLAS387A – NOVEMBER 2004 – REVISED DECEMBER 2004
Figure 47. Read Frame Controlled via FS (FS is High When BUSY Falls)
If another data frame is attempted by pulling up FS during an active data frame, then the ongoing frame is
aborted and a new frame is started.
The ADS8380 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution, which inherently includes a sample/hold function.
The device includes a built-in conversion clock, internal reference, and 40-MHz SPI compatible serial interface.
The maximum conversion time is 1.16 µ s which is capable of sustaining a 600-kHz throughput.
The analog input is provided to the two input pins: +IN and –IN. When a conversion is initiated, the differential
input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
The ADS8380 has a built-in 4.096-V (nominal value) reference but can operate with an external reference also.
When the internal reference is used, pin 9 (REFOUT) should be shorted to pin 8 (REFIN) and a 0.1-µF
decoupling capacitor and a 1-µF storage capacitor must be connected between pin 8 (REFIN) and pin 7 (REFM)
(see Figure 48 ). The internal reference of the converter is buffered.
20
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