Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 48

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FEATURES APPLICATIONS

DESCRIPTION

CDAC

Output

Latches

and

3-State

Drivers

BYTE

16-/8-Bit

Parallel DATA

Output Bus

SAR

Conversion

and

Control Logic

Comparator

Clock

+IN

−IN

REFIN

CONVST

BUSY

RESET

4.096-V

Internal

Reference

REFOUT

ADS8405

SLAS427 – DECEMBER 2004

16-BIT, 1.25-MSPS, UNIPOLAR PSEUDO-DIFFERENTIAL INPUT, MICROPOWER

SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE

• DWDM

• Unipolar Pseudo-Differential Input, 0 V to V

ref

• Instrumentation

• 16-Bit NMC at 1.25 MSPS

• High-Speed, High-Resolution, Zero Latency

• ± 2 LSB INL Max, -1/+1.5 LSB DNL

Data Acquisition Systems

• 86 dB SNR, -90 dB THD at 100 kHz Input

• Transducer Interface

• Zero Latency

• Medical Instruments

• Internal 4.096-V Reference

• Communications

• High-Speed Parallel Interface

• Single 5-V Analog Supply

• Wide I/O Supply: 2.7 V to 5.25 V

The ADS8405 is a 16-bit, 1.25-MHz A/D converter

with an internal 4.096-V reference. The device in-

• Low Power: 155 mW at 1.25 MHz Typ

cludes a 16-bit capacitor-based SAR A/D converter

• Pin Compatible With ADS8411/8401

with inherent sample and hold. The ADS8405 offers a

• 48-Pin TQFP Package

full 16-bit interface and an 8-bit option where data is

read using two 8-bit read cycles if necessary.

The ADS8405 has a unipolar pseudo-differential in-

put. It is available in a 48-lead TQFP package and is

characterized over the industrial -40 ° C to 85 ° C tem-

perature range.

High Speed SAR Converter Family

Type/Speed 500 kHz ~600 kHz 750 kHz 1 MHz 1.25 MHz 2 MHz 3 MHz 4 MHz

ADS8383 ADS8381

18-Bit Pseudo-Diff

ADS8380 (S)

18-Bit Pseudo-Bipolar, Fully Diff ADS8382 (S)

16-Bit Pseudo-Diff ADS8371 ADS8401/05 ADS8411

16-Bit Pseudo-Bipolar, Fully Diff ADS8402/06 ADS8412

14-Bit Pseudo-Diff ADS7890 (S) ADS7891

12-Bit Pseudo-Diff ADS7886 ADS7881

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

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ADS8405 SLAS427 – DECEMBER 2004 16-BIT, 1.25-MSPS, UNIPOLAR PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE FEATURES APPLICATIONS • • • • • • • • • • • • • • • Unipolar Pseudo-Differential Input, 0 V to Vref 16-Bit NMC at 1.25 MSPS ±2 LSB INL Max, -1/+1.5 LSB DNL 86 dB SNR, -90 dB THD at 100 kHz Input Zero Latency Internal 4.096-V Reference High-Speed Parallel Interface Single 5-V Analog Supply Wide I/O Supply: 2.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 ORDERING INFORMATION (1) MODEL MAXIMUM INTEGRAL LINEARITY (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) NO MISSING CODES RESOLUTION (BIT) PACKAGE TYPE PACKAGE DESIGNATOR TEMPERATURE RANGE ADS8405I –4 to +4 –2 to +2 15 48 Pin TQFP PFB –40°C to 85°C ADS8405IB (1) –2 to +2 –1 to +1.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input voltage (1) +IN – (–IN) Absolute input voltage 0 Vref +IN –0.2 Vref + 0.2 –IN –0.2 0.2 V V Input capacitance 25 pF Input leakage current 0.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 SPECIFICATIONS (continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 120 ms INTERNAL REFERENCE OUTPUT Internal reference start-up time From 95% (+VA), with 1-µF storage capacitor Vref range IOUT = 0 Source current Static load Line regulation +VA = 4.75 V to 5.25 V 0.6 mV Drift IOUT = 0 36 PPM/C 4.065 4.096 4.
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ADS8405 www.ti.
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ADS8405 www.ti.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 Terminal Functions NAME AGND BDGND NO. I/O DESCRIPTION 5, 8, 11, 12, 14, 15, 44, 45 – Analog ground 25, 35 – Digital ground for bus interface digital supply BUSY 36 O Status output. High when a conversion is in progress. BYTE 39 I Byte select input. Used for 8-bit bus reading. 0: No fold back 1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant pins DB[15:8]. CONVST 40 I Convert start.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 TIMING DIAGRAMS tw2 tw1 CONVST (used in normal conversion) tcycle CONVST (used in ABORT) tsu(AB) tpd1 tsu(AB) tpd2 tw4 tpd1 tw3 BUSY tsu1 tw7 td7 CS td6 CONVERT† tCONV tCONV SAMPLING† (When CS Toggle) tACQ BYTE tsu4 th1 tsu2 td1 th2 RD Data to be read† Invalid Previous Conversion th4 tdis ten tsu5 DB[15:8] Invalid Current Conversion Hi−Z Hi−Z D [15:8] DB[7:0] Hi−Z D [7:0] Hi−Z D [7:0] †Signal internal to device Figure 1.
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ADS8405 www.ti.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 TIMING DIAGRAMS (continued) tw1 tw2 CONVST (used in normal conversion) tcycle CONVST (used in ABORT) tsu(AB) tpd1 tsu(AB) tpd2 tw4 tpd1 tw3 BUSY CS = 0 CONVERT† tCONV tCONV t(ACQ) SAMPLING† (When CS = 0) BYTE tsu4 th1 th2 RD tdis ten Data to be read† th4 DB[15:8] DB[7:0] †Signal Invalid Invalid Previous Conversion Current Conversion tsu5 Hi−Z Hi−Z D [15:8] D [7:0] D [7:0] Hi−Z Hi−Z internal to device Figure 3.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 TIMING DIAGRAMS (continued) tw1 CONVST (used in normal conversion) tw2 tcycle CONVST (used in ABORT) tsu(AB) tpd1 tsu(AB) tpd2 tw4 tpd1 tpd2 tw3 BUSY CS = 0 CONVERT† tCONV tCONV tACQ SAMPLING† (When CS Toggle) th1 th1 BYTE RD = 0 td3 td3 td5 th4 tsu5 Previous MSB Invalid DB[15:8] Previous Previous LSB LSB Invalid DB[7:0] †Signal td5 th4 td3 tsu5 Invalid MSB LSB MSB MSB LSB MSB Invalid internal to device Figure 4.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 TYPICAL CHARACTERISTICS At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and fsample = 1.25 MHz (unless otherwise noted) SIGNAL-TO-NOISE RATIO vs FREE-AIR TEMPERATURE HISTOGRAM (DC Code Spread) HALF SCALE 131071 CONVERSIONS 86.8 80000 70000 60000 SNR − Signal-to-Noise Ratio − dB +VA = 5 V, +VBD = 3.3 V, TA = 25°C, Code = 65292 50000 40000 30000 20000 10000 86.4 86.2 86 85.8 85.6 85.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION vs FREE-AIR TEMPERATURE 95 −90 THD − Total Harmonic Distortion − dB SFDR − Spurious Free Dynamic Range − dB SPURIOUS FREE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 94 93 92 91 fi = 50 kHz, Full Scale Input, +VA = 5 V, +VBD = 3 V, Int Ref = 4.096 V 90 −40 −25 −10 5 20 35 50 65 −94 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 86.7 86.6 86.5 86.4 86.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 29 fi = 50 kHz, Full Scale Input, +VA = 5 V, +VBD = 3 V, Int Ref = 4.096 V −92 −93 −94 −95 −96 −97 −98 −99 0 27.5 27 26.5 26 25 250 10 20 30 40 50 60 70 80 90 100 fi − Input Frequency − kHz 750 1000 Figure 16. Figure 17. GAIN ERROR vs SUPPLY VOLTAGE OFFSET ERROR vs SUPPLY VOLTAGE +VBD = 3.3 V, TA = 25°C, Ext Ref = 4.096 V Offset Voltage − mV 0.25 0.05 0 −0.05 0.2 0.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) OFFSET ERROR vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 29.2 0.5 +VA = 5 V, +VBD = 3.3 V, Ext Ref = 4.096 V Offset Voltage − mV 0.4 0.35 0.3 0.25 0.2 0.15 0.1 28.8 28.6 28.4 28.2 28 0.05 0 −40 −25 −10 5 20 35 50 65 27.8 80 −40 −25 −10 35 50 65 Figure 22. Figure 23. DIFFERENTIAL NONLINEARITY vs FREE-AIR TEMPERATURE INTEGRAL NONLINEARITY vs FREE-AIR TEMPERATURE 80 1.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) DNL 2.5 +VA = 5 V, +VBD = 5 V, TA = 25°C, Ext Ref = 4.096 V 2 1.5 DNL − LSBs 1 0.5 0 −0.5 −1 −1.5 −2 −2.5 0 16384 32768 Code 49152 65536 Figure 28. INL 2.5 +VA = 5 V, +VBD = 5 V, TA = 25°C, Ext Ref = 4.096 V 2 1.5 INL − LSBs 1 0.5 0 −0.5 −1 −1.5 −2 −2.5 0 16384 32768 Code 49152 65536 Figure 29. FFT 0 +VA = 5 V, +VBD = 3.3 V, REF +32768 Points, fi = 100 kHz, fs = 1.25 MHz, TA = 25°C, Int Ref = 4.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 APPLICATION INFORMATION MICROCONTROLLER INTERFACING ADS8405 to 8-Bit Microcontroller Interface Figure 31 shows a parallel interface between the ADS8405 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V 0.1 µF AGND 10 µF Ext Ref Input 0.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 PRINCIPLES OF OPERATION (continued) The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. REFERENCE The ADS8405 can operate with an external reference with a range from 2.5 V to 4.2 V. A 4.096-V internal reference is included.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 PRINCIPLES OF OPERATION (continued) DIGITAL INTERFACE Timing And Control See the timing diagrams in the specifications section for detailed information on timing signals and their requirements. The ADS8405 uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter. No external clock input is required.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 RESET RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time is 25 ns. The current conversion is aborted no later than 50 ns after the converter is in reset mode. In addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation mode no later than 20 ns after the RESET input is brought high.
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ADS8405 www.ti.com SLAS427 – DECEMBER 2004 As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. Power to the ADS8405 should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible. See Table 2 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS8405IBPFBR TQFP PFB 48 ADS8405IBPFBT TQFP PFB ADS8405IPFBR TQFP PFB ADS8405IPFBT TQFP PFB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 48 250 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8405IBPFBR TQFP PFB 48 1000 367.0 367.0 38.0 ADS8405IBPFBT TQFP PFB 48 250 367.0 367.0 38.0 ADS8405IPFBR TQFP PFB 48 1000 367.0 367.0 38.0 ADS8405IPFBT TQFP PFB 48 250 367.0 367.0 38.
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MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.