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ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal VQFN 48

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FEATURES

APPLICATIONS

DESCRIPTION

CDAC

Output

Latches

and

3-State

Drivers

BYTE

16-/8-Bit

ParallelDA TA

OutputBus

SAR

Conversion

and

ControlLogic

Comparator

Clock

+IN

−IN

REFIN

CONVST

BUSY

4.096-V

Internal

Reference

REFOUT

BUS18/16

ADS8484

SLAS511 – NOVEMBER 2007

18-BIT, 1.25-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER

SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE,

REFERENCE

• 48-Pin 7x7 QFN Package

• 1.25-MHz Sample Rate

• ± 1.5 LSB Typ, ± 2.5 LSB Max INL

• Medical Instruments

• +0.8/-0.6 LSB Typ, +1.5/-1 LSB Max DNL

• Optical Networking

• 18-Bit NMC Ensured Over Temperature

• Transducer Interface

• ± 0.5-mV Offset Error

• High Accuracy Data Acquisition Systems

• ± 0.05-PPM/ ° C Offset Error Drift

• Magnetometers

• ± 0.1 %FSR Gain Error

• ± 0.5-PPM/ ° C Gain Error Drift

• 98.5dB SNR, – 120db THD, 121dB SFDR

The ADS8484 is an 18-bit, 1.25-MSPS A/C converter

with an internal 4.096-V reference and a

• Zero Latency

pseudo-bipolar, fully differential input. The device

• Low Power: 235 mW Typ at 1.25 MSPS

includes a 18-bit capacitor-based SAR A/D converter

• Pseudo-Bipolar Fully Differential Input Range:

with inherent sample and hold. The ADS8484 offers a

ref

to – V

ref

full 18-bit interface, a 16-bit option where data is read

using two read cycles, or an 8-bit bus option using

• Onboard Reference with 6 PPM/ ° C Drift

three read cycles.

• Onboard Reference Buffer

The ADS8484 is available in a 48-lead 7x7 QFN

• High-Speed Parallel Interface

package and is characterized over the industrial

• Wide Digital Supply 2.7 V to 5.25 V

– 40 ° C to 85 ° C temperature range.

• 8-/16-/18-Bit Bus Transfer

HIGH SPEED SAR CONVERTER FAMILY

TYPE/SPEED 500 kHz ~600 kHz 750 kHz 1 MHz 1.25 MHz 2 MHz 3 MHz 4MHz

ADS8383 ADS8381 ADS8481

18-Bit Pseudo-Diff

ADS8380 (s)

18-Bit Pseudo-Bipolar, Fully Diff ADS8382 (s) ADS8482 ADS8484

ADS8327 ADS8370 (s) ADS8371 ADS8471 ADS8401 ADS8411

16-Bit Pseudo-Diff

ADS8328 ADS8472 (s) ADS8405 ADS8410 (s)

ADS8472 ADS8402 ADS8412 ADS8422

16-Bit Pseudo-Bipolar, Fully Diff

ADS8406 ADS8413 (s)

14-Bit Pseudo-Diff ADS7890 (s) ADS7891

12-Bit Pseudo-Diff ADS7886 ADS7881

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

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ADS8484 SLAS511 – NOVEMBER 2007 18-BIT, 1.25-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE • 48-Pin 7x7 QFN Package 1.25-MHz Sample Rate APPLICATIONS ±1.5 LSB Typ, ±2.5 LSB Max INL • Medical Instruments +0.8/-0.6 LSB Typ, +1.5/-1 LSB Max DNL • Optical Networking 18-Bit NMC Ensured Over Temperature • Transducer Interface ±0.5-mV Offset Error • High Accuracy Data Acquisition Systems ±0.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 SPECIFICATIONS TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input voltage (1) Absolute input voltage +IN – (–IN) –Vref Vref +IN –0.2 Vref + 0.2 –IN –0.2 Vref + 0.2 (Vref)/2 – 0.2 (Vref)/2 (Vref)/2 + 0.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 SPECIFICATIONS (Continued) TA = –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, Vref = 4.096 V, fSAMPLE = 1.25 MSPS (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 3.0 4.096 +VA – 0.8 UNIT VOLTAGE REFERENCE INPUT Vref Reference voltage at REFIN Reference resistance (1) 500 Reference current drain fs = 1.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREE-AIR TEM PERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 48 47.6 +VA = 5 V, +VBD = 5 V, fi = 1.25 MSPS, Vref = 4.096 V 47 TA = 25°C, fi = 1.25 MSPS, Vref = 4.096 V 47.2 47.2 46.8 46.8 46.4 46 45.6 45.2 44.8 46.4 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C 44 4.75 80 45 44 43 42 41 40 44.4 46 -40 TA = 25°C, +VA = 5 V, +VBD = 5 V, Vref = 4.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) OFFSET ERROR vs FREE-AIR TEMPERATURE OFFSET ERROR vs SUPPLY VOLTAGE 0.04 0.06 0.1 TA = 25°C, fi = 1.25 MSPS, Vref = 4.096 V 0.08 0.02 -0.04 -0.06 0.02 0 -0.02 -0.04 +VA = 5 V, +VBD = 5 V, fi = 1.25 MSPS, Vref = 4.096 V -0.08 -0.1 -40 -25 -10 5 20 35 50 65 TA - Free-Air Temperature - °C -0.02 -0.04 -0.08 -0.08 -0.1 4.75 80 4.85 4.95 5.05 5.15 Supply Voltage - V -0.1 3 5.25 3.2 3.4 3.6 3.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE + DISTORTION vs REFERENCE VOLTAGE 98 97.5 97 96.5 96 3 3.2 3.4 3.6 3.8 4 Vref - Reference Voltage - V 4.2 99 98.5 98 -115 +VA = 5 V, +VBD = 5 V, fs = 1.25 MSPS, TA = 25°C, fi = 2 kHz 97.5 97 96.5 96 3 3.2 3.4 3.6 3.8 4 -116 -117 +VA = 5 V, +VBD = 5 V, fs = 1.25 MSPS, Vref = 4.096 V, fi = 2 kHz -118 -119 -120 -121 -122 -40 4.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) INL INL - LSBs 2.5 2 1.5 +VA = 5 V, +VBD = 5 V, TA = 25°C, fs = 1.25 MSPS, Vref = 4.096 V 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 -131072 -65536 0 Output Code Figure 29. 65536 131072 FFT Power - dB 0 -20 -40 +VA = 5 V, +VBD = 5 V, TA = 25°C, fs = 1.25 MSPS, fi = 1.9 kHz, Vref = 4.096 V -60 -80 -100 -120 -140 -160 -180 -200 0 100 200 300 f - Frequency - kHz Figure 30.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) TIMING DIAGRAMS tw2 tw1 CONVST tpd1 tpd2 tw4 tw3 BUSY tsu1 CS tpd3 tw7 td7 td6 CONVERT† t(CONV) t(CONV) t(HOLD) SAMPLING† (When CS Toggle) t(ACQ) tsu(ABORT) tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tsu5 tsu2 tpd4 th2 td1 RD tdis ten DB[17:12] Hi−Z D[17:12] Hi−Z D[9:4] MSB DB[11:10] DB[9:0] †Signal Hi−Z Hi−Z D[11:10] D[3:2] D[1:0] Hi−Z Hi−Z D[9:0] internal to device Figure 31.
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ADS8484 www.ti.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) tw1 tw2 CONVST tpd1 tpd2 tw4 tw3 BUSY CS = 0 CONVERT† t(CONV) t(CONV) t(HOLD) t(ACQ) SAMPLING† (When CS = 0) tsu(ABORT) tsu(ABORT) BYTE tsu5 th1 BUS 18/16 tsu5 tpd4 th2 RD tdis ten MSB DB[17:12] DB[11:10] DB[9:0] †Signal Hi−Z Hi−Z Hi−Z D[17:12] D[9:4] D[11:10] D[3:2] D[9:0] Hi−Z D[1:0] Hi−Z Hi−Z internal to device Figure 33.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) tw2 tw1 CONVST tpd1 tw4 tpd2 tw3 BUSY CS = 0 CONVERT† t(CONV) t(CONV) tpd3 tpd3 t(HOLD) t(HOLD) t(ACQ) SAMPLING† (When CS = 0) tsu(ABORT) tsu(ABORT) BYTE tsu5 tsu5 BUS 18/16 tsu5 tsu5 th1 th1 RD = 0 td5 DB[17:12] DB[11:10] D[17:12] Previous LSB DB[9:0] †Signal D[11:10] D[9:4] D[3:2] D[9:0] Next D[17:12] D[1:0] Next D[11:10] Next D[9:0] internal to device Figure 34.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 TYPICAL CHARACTERISTICS (continued) CS RD BYTE tsu5 BUS 18/16 ten ten DB[17:0] Hi−Z tdis Valid Hi−Z td3 tdis td3 Valid Valid Hi−Z Figure 35.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 APPLICATION INFORMATION MICROCONTROLLER INTERFACING ADS8484 to 8-Bit Microcontroller Interface Figure 36 shows a parallel interface between the ADS8484 and a typical microcontroller using the 8-bit data bus. The BUSY signal is used as a falling-edge interrupt to the microcontroller. Analog 5 V 0.1 µF AGND 10 µF Ext Ref Input 0.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 PRINCIPLES OF OPERATION The ADS8484 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 36 for the application circuit for the ADS8484. The conversion clock is generated internally. The conversion time of 610 ns is capable of sustaining a 1.25-MHz throughput.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 ANALOG INPUT When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the internal capacitor array. Both +IN and –IN input has a range of –0.2 V to Vref + 0.2 V. The input span [+IN – (–IN)] is limited to –Vref to Vref. The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source impedance.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 +12 V 1 mF R +VIN 5W +0V to +4V C THS4031 1 mF (+)IN 1 mF -12 V 75 W 2200 pF 300 W +12 V 1 mF 300 W 5W THS4031 (-)IN +2.048 V 1 mF 1 mF -12 V Figure 40. Single-Ended Input, Differential Output Configuration In systems, where the input is differential, the THS4031 can be used in the inverting configuration with an additional DC bias applied to its + input so as to keep the input to the ADS8484 within its rated operating voltage range.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 +12 V 1 mF +1.024 V ... (Vref/4) 5W 300 W THS4031 (+)IN -2.048 V to +2.048 V 1 mF 1 mF -12V AP Cascade Two System 2200 pF 300 W AP Cascade Two System Pattern Generator Platform fi = 1 kHz SNR: 98.5 dB SINAD: 98.5 dB THD: -117 dB SFDR: 120 dB ENOB(SINAD): 16 +2.048 V to -2.048 V 300 W +12V 1 mF 300 W 5W THS4031 (-)IN +1.024 V ... (Vref/4) 1 mF 1 mF -12 V Figure 41.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8484 switches from the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal is important to the performance of the converter. The BUSY output is brought high immediately following CONVST going low.
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ADS8484 www.ti.com SLAS511 – NOVEMBER 2007 RESET On power-up, internal POWER-ON RESET circuitry generates the reset required for the device. The first three conversions after power-up are used to load factory trimming data for a specific device to assure high accuracy of the converter. The results of the first three conversions are invalid and should be discarded. The device can also be reset through the use of the combination fo CS and CONVST.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS8484IBRGZR VQFN RGZ 48 ADS8484IBRGZT VQFN RGZ ADS8484IRGZR VQFN RGZ ADS8484IRGZT VQFN RGZ SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 250 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 48 1000 330.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8484IBRGZR VQFN RGZ 48 1000 336.6 336.6 28.6 ADS8484IBRGZT VQFN RGZ 48 250 336.6 336.6 28.6 ADS8484IRGZR VQFN RGZ 48 1000 336.6 336.6 28.6 ADS8484IRGZT VQFN RGZ 48 250 336.6 336.6 28.
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