Datasheet

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TIMING DIAGRAMS
MSB
Hi−Z Hi−Z
t
w1
CONVST
t
pd1
t
pd2
t
w4
t
su1
BUSY
CS
CONVERT
†
t
(CONV)
SAMPLING
†
(When CS Toggle)
BYTE
t
w2
t
w3
t
(ACQ)
t
h1
t
pd4
t
en
BUS 18/16
RD
DB[17:12]
t
d1
t
dis
t
h2
t
su2
t
(CONV)
†
Signal internal to device
DB[11:10]
DB[9:0]
D[9:0]
D[11:10] D[3:2] D[1:0]
D[17:12] D[9:4]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
t
d6
t
su5
t
su5
t
su(ABORT)
t
su(ABORT)
t
d7
t
w7
t
pd3
t
(HOLD)
ADS8484
SLAS511 – NOVEMBER 2007
TYPICAL CHARACTERISTICS (continued)
Figure 31. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
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