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DB[17:12]
MSB
Hi−Z
Hi−Z
Hi−Z
CONVST
BUSY
CS
CONVERT
†
SAMPLING
†
(When CS Toggle)
BYTE
BUS 18/16
RD = 0
t
w1
t
pd1
t
pd2
t
w4
t
w2
t
w3
t
su1
t
(CONV)
t
(ACQ)
t
(CONV)
t
h1
t
pd4
t
en
t
h2
t
dis
†
Signal internal to device
t
d6
t
su5
t
dis
Hi−Z
Hi−Z
t
en
Previous
Previous
Repeated
Repeated
D [9:0]
Hi−Z
Previous
Repeated
t
d7
t
pd3
t
(HOLD)
t
en
Hi−Z
Hi−Z
DB[11:10]
D[11:10]
D[3:2] D[1:0]
D[17:12] D[9:4]
Hi−Z
DB[9:0]
D[9:0]
D [9:0]
t
w7
t
su(ABORT)
t
su(ABORT)
D[17:12]
D[17:12]
D[11:10] D[11:10]
ADS8484
SLAS511 – NOVEMBER 2007
TYPICAL CHARACTERISTICS (continued)
Figure 32. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): ADS8484