Datasheet

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BYTE
BUS 18/16
RD
t
h1
t
pd4
t
h2
t
en
t
dis
†
Signal internal to device
MSB
Hi−Z Hi−Z
DB[17:12]
DB[11:10]
DB[9:0]
D[9:0]
D[11:10] D[3:2] D[1:0]
D[17:12] D[9:4]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
t
su5
t
su5
CONVST
BUSY
CS = 0
CONVERT
†
SAMPLING
†
(When CS = 0)
t
w1
t
pd2
t
pd1
t
w4
t
w2
t
w3
t
(CONV)
t
(ACQ)
t
(HOLD)
t
su(ABORT)
t
su(ABORT)
t
(CONV)
ADS8484
SLAS511 – NOVEMBER 2007
TYPICAL CHARACTERISTICS (continued)
Figure 33. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
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Product Folder Link(s): ADS8484