Datasheet

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+12V
-12V
+1.024V...(V /4)
ref
THS4031
2200pF
(+)IN
-2.048Vto+2.048V
+12V
-12V
THS4031 (-)IN
+1.024V...(V /4)
ref
+2.048Vto-2.048V
AP Cascade
TwoSystem
AP Cascade TwoSystem
PatternGeneratorPlatform
f =1kHz
i
SNR:98.5dB
SINAD:98.5dB
THD:-117dB
SFDR:120dB
ENOB(SINAD):16
1 Fm
1 Fm
1 Fm
1 Fm
1 Fm
1 Fm
5 W
300 W
300 W
300 W
5 W
300 W
DIGITAL INTERFACE
Timing and Control
ADS8484
SLAS511 – NOVEMBER 2007
Figure 41. Differential Input, Differential Output Configuration
See the timing diagrams in the specifications section for detailed information on timing signals and their
requirements.
The ADS8484 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS8484