Datasheet
www.ti.com
TIMING CHARACTERISTICS
ADS8484
SLAS511 – NOVEMBER 2007
All specifications typical at – 40 ° C to 85 ° C, +VA = 5 V +VBD = 3 V
(1) (2) (3)
PARAMETER MIN TYP MAX UNIT
t
(CONV)
Conversion time 610 ns
t
(ACQ)
Acquisition time 175 ns
t
(HOLD)
Sample capacitor hold time 15 ns
t
pd1
CONVST low to BUSY high 40 ns
t
pd2
Propagation delay time, end of conversion to BUSY low 15 ns
t
pd3
Propagation delay time, start of convert state to rising edge of BUSY 25 ns
t
w1
Pulse duration, CONVST low 40 ns
t
su1
Setup time, CS low to CONVST low 20 ns
t
w2
Pulse duration, CONVST high 20 ns
CONVST falling edge jitter 10 ps
t
w3
Pulse duration, BUSY signal low t
(ACQ)
min ns
t
w4
Pulse duration, BUSY signal high 610 ns
t
h1
Hold time, first data bus transition ( RD low, or CS low for read cycle, or BYTE or
40 ns
BUS18/ 16 input changes) after CONVST low
t
d1
Delay time, CS low to RD low 0 ns
t
su2
Setup time, RD high to CS high 0 ns
t
w5
Pulse duration, RD low 50 ns
t
en
Enable time, RD low (or CS low for read cycle) to data valid 30 ns
t
d2
Delay time, data hold from RD high 5 ns
t
d3
Delay time, BUS18/ 16 or BYTE rising edge or falling edge to data valid 10 30 ns
t
w6
Pulse duration, RD high 20 ns
t
w7
Pulse duration, CS high 20 ns
t
h2
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge 50 ns
t
pd4
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
0 ns
edge
t
d4
Delay time, BYTE edge to BUS18/ 16 edge skew 0 ns
t
su3
Setup time, BYTE or BUS18/ 16 transition to RD falling edge 10 ns
t
h3
Hold time, BYTE or BUS18/ 16 transition to RD falling edge 10 ns
t
dis
Disable time, RD high ( CS high for read cycle) to 3-stated data bus 30 ns
t
d5
Delay time, BUSY low to MSB data valid delay 0 ns
t
d6
Delay time, CS rising edge to BUSY falling edge 50 ns
t
d7
Delay time, BUSY falling edge to CS rising edge 50 ns
t
su5
BYTE transition setup time, from BYTE transition to next BYTE transition, or BUS18/ 16
50 ns
transition setup time, from BUS18/ 16 to next BUS18/ 16.
t
su(ABORT)
Setup time from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST are used to abort) or to the 70 480 ns
next falling edge of CS (when CS is used to abort).
(1) All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) See timing diagrams.
(3) All timing are measured with 20-pF equivalent loads on all data bits and BUSY pins.
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Product Folder Link(s): ADS8484