Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 28

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FEATURES APPLICATIONS

DESCRIPTION

Successive ApproximationRegisterandControlLogic

Clock

BUSY

Comparator

BYTE

R/C

CDAC

Buffer

REF

CAP

± 10VInput

5kΩ

2k

Ω

9.8kΩ

Internal

+2.5VRef

4kΩ

Output

Latches

and

Three

State

Drivers

Three

State

Parallel

Data

Bus

ADS8505

SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007

16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER

• Industrial Process Control

• 105dB SFDR at 250-kHz Sample Rate

• Data Acquisition Systems

• Standard ± 10-V Input Range

• Digital Signal Processing

• ± 1.5 LSB Max INL

• Medical Equipment

• ± 1 LSB Max DNL, 16-Bits No Missing Codes

• Instrumentation

• ± 2 mV Max Bipolar Zero Error With ± 0.4

PPM/ ° C Drift

• ± 0.1% FSR Max Full-Scale Error With ± 2

The ADS8505 is a complete 16-bit sampling A/D

PPM/ ° C Drift

converter using state-of-the-art CMOS structures. It

• Single 5-V Supply Operation

contains a complete 16-bit, capacitor-based, SAR

• Pin-Compatible With ADS7805 (Low Speed)

A/D with S/H, reference, clock, interface for

and 12-Bit ADS8504/7804

microprocessor use, and 3-state output drivers.

• Uses Internal or External Reference

The ADS8505 is specified at a 250-kHz sampling

• Full Parallel Data Output rate over the full temperature range. Precision

resistors provide an industry standard ± 10-V input

• 70-mW Typ Power Dissipation at 250 KSPS

range, while the innovative design allows operation

• 28-Pin SSOP and SOIC Packages

from a single +5-V supply, with power dissipation

under 100 mW.

The ADS8505 is available in 28-pin SOIC and 28-pin

SSOP packages, both fully specified for operation

over the industrial –40 ° C to 85 ° C temperature range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
ADS8505 SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • 105dB SFDR at 250-kHz Sample Rate Standard ±10-V Input Range ±1.5 LSB Max INL ±1 LSB Max DNL, 16-Bits No Missing Codes ±2 mV Max Bipolar Zero Error With ±0.4 PPM/°C Drift ±0.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM RELATIVE ACCURACY (LSB) ADS8505IB NO MISSING CODE ±1.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted) ADS8505I PARAMETER ADS8505IB TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX DC ACCURACY INL Integral linearity error –4 4 –1.5 1.5 LSB (1) DNL Differentiall linearity error –2 2 –1 1 LSB (1) No missing codes 15 Transition noise (2) 0.77 Full-scale error (3) (4) Int. ref.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 85°C, fs = 250 kHz, VDIG = VANA = 5 V, using internal reference (unless otherwise noted) ADS8505I PARAMETER ADS8505IB TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX DIGITAL TIMING Bus access timing 83 83 ns Bus relinquish timing 83 83 ns V POWER SUPPLIES VDIG Digital input voltage 4.75 5 5.25 4.75 5 5.25 VANA Analog input voltage 4.75 5 5.25 4.75 5 5.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 DEVICE INFORMATION (continued) Terminal Functions TERMINAL NAME DB/DW NO. DIGITAL I/O DESCRIPTION AGND1 2 Analog ground. Used internally as ground reference point. AGND2 5 Analog ground. BUSY 26 O At the start of a conversion, BUSY goes low and stays low until the conversion is completed and the digital outputs have been updated. BYTE 23 I Selects 8 most significant bits (low) or 8 least significant bits (high).
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS 100 95 90 fs = 250 KSPS, fi = 20 kHz 85 -20 0 20 40 60 TA - Free-Air Temperature - ºC -95 -90 -85 fs = 250 KSPS -80 fi = 20 kHz -20 0 20 40 60 TA - Free-Air Temperature - º C fs = 250 KSPS 95 fi = 20 kHz 90 85 80 75 70 -40 80 -20 0 20 40 60 Figure 2. Figure 3.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) NEGATIVE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 0.25 4 0.2 3 2 1 0 −1 −2 −3 −4 −5 −40 −20 0 20 40 60 TA − Free-Air Temperature − 5C External Reference 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 −20 0 20 40 60 TA − Free-Air Temperature − 5C 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 −40 80 −20 0 20 40 60 TA − Free-Air Temperature − 5C Figure 10. Figure 11. Figure 12.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) INTEGRAL NONLINEARITY 1.5 INL - LSBs 1 0.5 0 -0.5 -1 -1.5 0 16384 32768 Code Figure 18. 49152 65536 49152 65536 DIFFERENTIAL NONLINEARITY 1 DNL - LSBs 0.5 0 -0.5 -1 0 16384 32768 Code Figure 19. FFT (20-kHz Input) Amplitude - dB 20 0 -20 8192 Points fs = 250 KSPS fi = 20 KHz, 0dB SINAD = 87.7 dB THD = -103.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 BASIC OPERATION (continued) The ADS8505 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convert commands assures accurate acquisition of a new signal. The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the CALIBRATION section).
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 200 Ω 1 28 2 27 3 26 4 25 5 24 B15 (MSB) 6 23 B14 7 B13 33.2 kΩ + 2.2 µF 2.2 µF + + 0.1 µF +5V + 10 µF Convert Pulse 22 B0 (LSB) 8 21 B1 B12 9 20 B2 B11 10 19 B3 B10 11 18 B4 B9 12 17 B5 B8 13 16 B6 14 15 B7 ADS8505 40 ns Min Figure 21. Basic Operation READING DATA The ADS8505 outputs full or byte-reading parallel data in binary 2's complement data output format.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 The number of control lines can be reduced by tying CS low while using the falling edge of R/C to initiate conversions and the rising edge of R/C to activate the output mode of the converter. See Figure 23. Table 3. Conversion Timing SYMBOL DESCRIPTION MIN TYP tw1 Pulse duration, convert ta Access time, data valid after R/C low 2.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 tw1 R/C tc ta1 tw2 BUSY tpd td2 td1 Acquire MODE Convert Acquire tconv DATA BUS Previous Data Valid Previous Data Valid Hi−Z Convert tacq Not Valid Data Valid Hi−Z Data Valid td3 tdis tv Figure 23. Conversion Timing with Outputs Enabled after Conversion (CS Tied Low) tsu tsu tsu tsu R/C tw1 CS tpd tw2 BUSY td2 MODE Acquire Convert Acquire tconv Hi−Z State DATA BUS Data Valid ten Hi−Z State tdis Figure 24.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 tc tw1 tw1 R/C tpd tpd BUSY 0 ns MIN 4.75V VANA VDIG DATA BUS Unknown Hi-Z Not Valid Hi-Z Not Valid Data Valid td3 Figure 26. ADC Reset ADC RESET The ADC reset function of the ADS8505 can be used to terminate the current conversion cycle. Bringing R/C low for at least 40 ns while BUSY is low will initiate the ADC reset.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 +15V 2.2 mF 22 pF ADS8505 200 W 100 nF GND VIN 2 kW Pin 7 2 kW Vin Pin 2 22 pF Pin3 Pin 1 − OPA 627 or OPA 132 + REF 2.2 mF 33.2 kW Pin 6 AGND1 Pin4 GND CAP 2.2 mF GND 100 nF 2.2 mF DGND GND AGND2 −15 V GND Figure 27.
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ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 APPLICATION INFORMATION CALIBRATION The ADS8505 can be trimmed in hardware or software. The offset should be trimmed before the gain since the offset directly affects the gain. To achieve optimum performance, several iterations may be required. Hardware Calibration To calibrate the offset and gain of the ADS8505, install the proper resistors and potentiometers as shown in Figure 28(a).
PAGE 16
ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 APPLICATION INFORMATION (continued) CAP CAP (pin 4) is the output of the internal reference buffer. A 2.2-µF capacitor can be placed between the CAP pin and ground. Because the internal reference buffer is internally compensated, the external capacitor is not necessary for compensation of the reference buffer. This relaxes the performance requirements of the capacitor and makes the performance of the ADC less sensitive to the capacitor.
PAGE 17
ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 Intermediate latches are beneficial on any monolithic A/D converter. The ADS8505 has an internal LSB size of 38 µV. Transients from fast switching signals on the parallel port, even when the A/D is 3-stated, can be coupled through the substrate to the analog circuitry causing degradation of converter performance.
PAGE 18
ADS8505 www.ti.com SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September, 2005) to A Revision ............................................................................................. Page • • • • • • • Added SFDR value .....................................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8505IBDBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1 ADS8505IBDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 ADS8505IDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8505IBDBR SSOP DB 28 2000 367.0 367.0 38.0 ADS8505IBDWR SOIC DW 28 1000 367.0 367.0 55.0 ADS8505IDWR SOIC DW 28 1000 367.0 367.0 55.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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