Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SOIC 28

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FEATURES APPLICATIONS

DESCRIPTION

Successive Approximation Register

Clock

Comparator

CDAC

Buffer

REF

CAP

40 kΩ

9.9 kΩ

Internal

+2.5 V Ref

6 kΩ

Parallel

and

Serial

Data

Out

Control

BUSYBUSY

DATACLK

TAG

20 kΩ

39.8 kΩ

EXT/IN

R/C

SB/BTC

BYTE

REFD

Parallel

Data

PWRD

SDATA

ADS8507

SLAS381 – DECEMBER 2006

16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH

INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE

• Industrial Process Control

• 40-kHz Min Sampling Rate

• Test Equipment

• 4-V, 5-V, and ±10-V Input Ranges

• Medical Equipment

• 89.9-dB SINAD with 10-kHz Input

• Data Acquisition Systems

• ±1.5 LSB Max INL

• Digital Signal Processing

• +1.5/–1 LSB Max DNL, 16-Bit No Missing

• Instrumentation

Codes

• ±5-mV BPZ, ±0.4 PPM/°C BPZ Drift

• SPI Compatible Serial Output With

The ADS8507 is a complete low power, single 5-V

Daisy-Chain (TAG) Feature

supply, 16-bit sampling analog-to-digital (A/D)

• Single 5-V Analog Supply

converter. It contains a complete 16-bit

• Pin-Compatible With ADS7807 and 12-Bit

capacitor-based, successive approximation register

(SAR) A/D converter with sample and hold, clock,

ADS7806/8506

reference, and data interface. The converter can be

• Uses Internal or External 2.5-V Reference

configured for a variety of input ranges including ±10

• Low Power Dissipation

V, 4 V, and 5 V. For most input ranges, the input

– 24 mW Typ, 30 mW Max at 40 KSPS

voltage can swing to 25 V or –25 V without damage

to the converter.

• 50-µW Max Power Down Mode

A SPI compatible serial interface allows data to be

• 28-Pin SO Package

synchronized to an internal or external clock. A full

• Full Parallel Interface

parallel interface with BYTE select is also provided to

• 2's Comp or BTC Output Code

allow the maximum system design flexibility. The

ADS8507 is specified at 40 kHz sampling rate over

the industrial -40 °C to 85 °C temperature range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

QSPI, SPI are trademarks of Motorola.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

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ADS8507 SLAS381 – DECEMBER 2006 16-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • 40-kHz Min Sampling Rate 4-V, 5-V, and ±10-V Input Ranges 89.9-dB SINAD with 10-kHz Input ±1.5 LSB Max INL +1.5/–1 LSB Max DNL, 16-Bit No Missing Codes ±5-mV BPZ, ±0.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION (1) PRODUCT MINIMUM RELATIVE ACCURACY (LSB) NO MISSING CODE MINIMUM SINAD (dB) SPECIFICATION TEMPERATURE RANGE PACKAGE LEAD PACKAGE DESIGNATOR ADS8507IB ±1.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS (continued) At TA = -40°C to 85°C, fS = 40 kHz, VDIG = VANA = 5 V, and using internal reference and fixed resistors, (see Figure 43) unless otherwise specified. PARAMETER DNL TEST CONDITIONS ADS8507I MIN Differential linearity error -2 No missing codes 15 Transition noise (2) TYP ADS8507IB MAX 3 MIN -1 -0.5 Full scale error drift Ext. 2.5-V Ref Full scale error drift Ext. 2.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 ELECTRICAL CHARACTERISTICS (continued) At TA = -40°C to 85°C, fS = 40 kHz, VDIG = VANA = 5 V, and using internal reference and fixed resistors, (see Figure 43) unless otherwise specified. PARAMETER IIH High-level input current TEST CONDITIONS ADS8507I MIN TYP VIH = 5 V ADS8507IB MAX MIN TYP ±10 MAX UNIT ±10 µA 0.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 DEVICE INFORMATION (continued) Terminal Functions TERMINAL NO. NAME DIGITAL I/O DESCRIPTION 1 R1IN Analog Input. 2 AGND1 Analog sense ground. Used internally as ground reference point. Minimal current flow 3 R2IN Analog Input. 4 CAP Reference buffer output. 2.2-µF Tantalum capacitor to ground. 5 REF Reference input/output. Outputs internal 2.5-V reference. Can also be driven by external system reference. In both cases, bypass to ground with a 2.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 Table 1. Input Range Connections (see Figure 42 and Figure 43) ANALOG INPUT RANGE CONNECT R1IN VIA 200 Ω TO CONNECT R2IN VIA 100 Ω TO IMPEDANCE ±10 V VIN CAP 45.7 kΩ 0 V to 5 V AGND VIN 20.0 kΩ 0 V to 4 V VIN VIN 21.4 kΩ TYPICAL CHARACTERISTICS POWER SUPPLY CURRENT vs FREE-AIR TEMPERATURE INTERNAL REFERENCE vs FREE-AIR TEMPERATURE POWER SUPPLY CURRENT vs SAMPLING FREQUENCY 2.520 6 6 5 4.5 Power Supply Current - mA 5.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) UNIPOLAR OFFSET ERROR vs FREE-AIR TEMPERATURE UNIPOLAR FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 3 0 0.2 2 1 0 -1 0.1 0 -0.1 Unipolar Range, 5 V Input Range -0.1 -0.2 -0.3 -0.4 -45 -30 -15 0 15 30 45 60 75 90 105 120 TA - Free-Air Temperature - ºC -0.2 -45 -30 -15 0 15 30 45 60 75 90 105 120 TA - Free-Air Temperature - ºC -2 -45 -30 -15 0 15 30 45 60 75 90 105 120 TA - Free-Air Temperature - ºC Figure 7.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) SIGNAL-TO-NOISE AND DISTORTION vs FREQUENCY SIGNAL-TO-NOISE RATIO vs FREQUENCY 90 80 70 60 0 1 10 100 f - Frequency - kHz 100 70 60 0 1 10 100 f - Frequency - kHz fi = 0 dB 100 90 80 70 1000 0 1 10 100 f - Frequency - kHz 1000 Figure 17. Figure 18.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) CONVERSION TIME vs FREE-AIR TEMPERATURE tCONVERT - Conversion Time - ms 18.1 18 17.9 17.8 17.7 17.6 17.5 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - °C Figure 25. INL 1.5 1 INL - Bits 0.5 0 -0.5 -1 -1.5 0 8192 16384 24576 32768 40960 49152 57344 65535 49152 57344 65535 Code Figure 26. DNL 1.5 DNL - Bits 1 0.5 0 -0.5 -1 0 8192 16384 24576 32768 40960 Code Figure 27.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 TYPICAL CHARACTERISTICS (continued) FFT 0 -10 8192 Point FFT; fI = 10 kHz, 0 dB -20 -30 Amplitude - dB -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 f - Frequency - kHz 15 20 Figure 28. FFT 0 -10 8192 Point FFT; fI = 20 kHz, 0 dB -20 Amplitude - dB -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 10 f - Frequency - kHz 15 20 Figure 29.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 BASIC OPERATION (continued) stay LOW until the conversion is completed and the output register is updated. If BYTE (pin 21) is LOW, the eight most significant bits (MSBs) will be valid when BUSY rises; if BYTE is HIGH, the eight least significant bits (LSBs) will be valid when BUSY rises. Data will be output in binary 2's complement (BTC) format. BUSY going HIGH can be used to latch the data.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 BASIC OPERATION (continued) Serial Output 200 Ω ± 10 V 66.5 kΩ +5V 100 Ω 2.2 µF 22 µF + + 1 28 2 27 3 26 4 25 5 24 6 23 7 22 ADS8507 + 0.1 µF + +5 V 10 µF BUSY Convert Pulse R/C 8 21 NC(1) 9 20 NC(1) 10 19 SDATA 11 18 DATACLK NC(1) NC(1) 12 17 NC(1) NC(1) 13 16 NC(1) 14 15 NC(1) 40 ns Min Figure 32.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 CS and R/C are internally ORed and level triggered. It is not a requirement which input goes low first when initiating a conversion. If, however, it is critical that CS or R/C initiates conversion N, be sure the less critical input is low at least tsu2 ≥ 10 ns prior to the initiating input. If EXT/INT (pin 8) is low when initiating conversion N, serial data from conversion N–1 is output on SDATA (pin 19) following the start of conversion N.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 PARALLEL OUTPUT To use the parallel output, tie EXT/INT (pin 8) high and DATACLK (pin 18) low. SDATA (pin 19) should be left unconnected. The parallel output is active when R/C (pin 22) is high and CS (pin 23) is low. Any other combination of CS and R/C 3-states the parallel output. Valid conversion data can be read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When BYTE (pin 21) is low, the 8 most significant bits will be valid with the MSB on D7.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 t21 t21 t1 t21 t21 R/C t21 t21 CS t3 t4 BUSY t21 t21 BYTE t21 Data Bus Hi-Z State High Byte t21 t9 t21 Hi-Z State t21 Low Byte Hi-Z State t9 Figure 34. CS to Control Conversion and Read Timing With Parallel Outputs PARALLEL OUTPUT (During a Conversion) After conversion N has been initiated, valid data from conversion N–1 can be read and is valid up to 12 µs after the start of conversion N.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 Table 5. Conversion and Data Timing, TA = -40°C to 85°C (continued) t21 R/C to CS setup time 10 t22 Valid data after DATACLK high 25 t7 + t8 Throughput time ns ns 25 µs SERIAL OUTPUT Data can be clocked out with the internal data clock or an external data clock. When using serial output, be careful with the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these pins come out of Hi-Z state whenever CS (pin 23) is low and R/C (pin 22) is high.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 Table 6. Timing Requirements, TA = –40°C to 85°C PARAMETER MIN TYP µs Pulse duration, convert td1 Delay time, BUSY from R/C low 12 20 ns tw2 Pulse duration, BUSY low 18 20 µs td2 Delay time, BUSY, after end of conversion td3 Delay time, aperture Conversion time tacq Acquisition time 12 UNIT tw1 tconv 0.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 tw1 tw1 R/C td1 td1 tw2 tw2 BUSY td2 td3 STATUS Error Correction Nth Conversion td2 td11 td3 td11 Error (N+1)th Conversion Correction (N+1)th Accquisition tconv tconv tacq tc1 td4 (N+2)th Accquisition tacq td4 Internal 1 DATACLK 2 16 td5 SDATA 2 1 16 td6 D15 TAG = 0 TAG = 0 D0 D15 D0 TAG = 0 Nth Conversion Data (N−1)th Conversion Data CS, EXT/INT, and TAG are tied low 8 starts READ Figure 36.
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ADS8507 www.ti.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 The preferred timing uses the discontinuous, external, data clock during the sampling period. Data must be read during the sampling period because there is not sufficient time to read data from multiple converters during a conversion period without violating the td11 constraint (see the EXTERNAL DATACLOCK section). The sampling period must be sufficiently long to allow all data words to be read before starting a new conversion.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 INPUT RANGES (continued) +15V 2.2 mF 22 pF ADS8507 200 W 100 nF GND R1IN 2 kW Pin 7 2 kW Vin Pin 2 22 pF Pin3 AGND1 Pin 1 100 W − OPA 627 or OPA 132 + R2IN Pin 6 33.2 kW GND R3IN Pin4 CAP 2.2 mF GND REF 2.2 mF GND 100 nF DGND 2.2 mF GND AGND2 −15 V GND Figure 41. Typical Driving Circuit (±10 V, No Trim) CALIBRATION Hardware Calibration To calibrate the offset and gain of the ADS8507 in hardware, install the resistors shown in Figure 42.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 Software Calibration To calibrate the offset and gain in software, no external resistors are required. However, to get the data sheet specifications for offset and gain, the resistors shown in Figure 43 are necessary. See the No Calibration section for more details on the external resistors. Refer to Table 8 for the range of offset and gain errors with and without the external resistors. ±10 V VIN 0 V to 5 V 200 Ω 1 2 66.5 kΩ 200 Ω 100 Ω 4 + 2.2 µF 5 + 2.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 (a) Bipolar (b) Unipolar Digital Output Digital Output + Full-Scale + Full-Scale Analog Input − Full-Scale Analog Input − Full-Scale Typical Transfer Functions With External Resistors. Typical Transfer Functions Without External Resistors. Figure 44. Typical Transfer Functions With and Without External Resistors To further analyze the effects of removing any combination of the external resistors, consider Figure 45.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 REFERENCE The ADS8507 can operate with its internal 2.5-V reference or an external reference. By applying an external reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally with the output on CAP (pin 4). The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error (FSE = ±0.5% for low grade, ±0.25% for high grade).
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 REFERENCE (continued) 7000 Power−Up Time − ms 6000 5000 4000 3000 2000 1000 0 0.1 1 10 CAP − Pin Value − mF 100 Figure 47. Power-Down to Power-Up Time vs Capacitor Value on CAP The output of the buffer is capable of driving up to 1 mA of current to a DC load. Using an external buffer allows the internal reference to be used for larger DC loads and AC loads. Do not attempt to directly drive an AC load with the output voltage on CAP.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 LAYOUT (continued) from the digital logic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the rest of the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used. Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filter the supply.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 APPLICATION INFORMATION TRANSITION NOISE Apply a DC input to the ADS8507 and initiate 1000 conversions. The digital output of the converter varies in output codes due to the internal noise of the ADS8507. This is true for all 16-bit SAR converters. The transition noise specification found in the electrical characteristics section is a statistical figure which represents the one sigma limit or rms value of these output codes.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 APPLICATION INFORMATION (continued) Convert Pulse QSPI ADS8507 R/C PCS0/SS MOSI SCK BUSY SDATA DATACLK CS EXT/INT BYTE CPOL = 0 (Inactive State is LOW) CPHA = 1 (Data Valid on Falling Edge) QSPI Port is in Slave Mode. Figure 49. QSPI Interface to the ADS8507 Before enabling the QSPI interface, the microcontroller must be configured to monitor the slave select line.
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ADS8507 www.ti.com SLAS381 – DECEMBER 2006 APPLICATION INFORMATION (continued) For the fastest conversion rate, the baud rate should be set to 2 (4.19-MHz SCK), DT set to 10, the first serial transfer set to 8 bits, the second set to 16 bits, and DSCK disabled (in the command control byte). This allows for a 23-kHz maximum conversion rate. For slower rates, DT should be increased.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8507IBDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1 ADS8507IDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8507IBDWR SOIC DW 28 1000 367.0 367.0 55.0 ADS8507IDWR SOIC DW 28 1000 367.0 367.0 55.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.