Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TQFP 48

FEATURES

● SELF-CALIBRATING

● HIGH SFDR: 85dB at NYQUIST

● HIGH SNR: 76dB

● LOW POWER: 250mW

●

DIFFERENTIAL OR SINGLE-ENDED INPUTS

●

+3V/+5V LOGIC I/O COMPATIBLE

● FLEXIBLE INPUT RANGE

● OVER-RANGE INDICATOR

● INTERNAL OR EXTERNAL REFERENCE

APPLICATIONS

● IF AND BASEBAND DIGITIZATION

● CCD IMAGING SCANNERS

● TEST INSTRUMENTATION

● IR IMAGING

DESCRIPTION

The ADS850 is a high dynamic range, 14-bit Analog-to-Digital

Converter (ADC) that utilizes a fully differential input, allowing for

either single-ended or differential input interface over varying

input spans. This converter features digital error correction tech-

niques ensuring 14-bit linearity and a calibration procedure that

corrects for capacitor and gain mismatches. The ADS850 also

includes a high-bandwidth track-and-hold that provides excellent

spurious performance up to and beyond the Nyquist rate.

The ADS850 provides an internal reference that can be pro-

grammed for a 2Vp-p input range for the best spurious perfor-

mance and ease of driving. Alternatively, the 4Vp-p input range

can be used for the lowest input referred noise, offering

superior signal-to-noise performance for imaging applications.

There is also the capability to set the range between 2Vp-p and

4Vp-p, or to use an external reference. The ADS850 also

provides an over-range indicator flag to indicate if the input has

exceeded the full-scale input range of the converter.

The low distortion and high signal-to-noise performance pro-

vide the extra margin needed for communications, imaging,

and test instrumentation applications. The ADS850 is available

in a TQFP-48 package.

14-Bit

Pipelined

ADC Core

Reference and

Mode Select

Reference Ladder

and Driver

Timing Circuitry

Error

Correction

Logic

and

Calibration

Circuitry

3-State

Outputs

T&H

D13

•

CLK

ADS850

VDRV

SEL REFBV

REF

REFT

INV

(Opt.)

OVR

14-Bit, 10MSPS Self-Calibrating

ANALOG-TO-DIGITAL CONVERTER

ADS850

SBAS154C – OCTOBER 2000 – REVISED OCTOBER 2002

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS850

Summary of content (17 pages)

PAGE 1
ADS850 ADS 850 SBAS154C – OCTOBER 2000 – REVISED OCTOBER 2002 14-Bit, 10MSPS Self-Calibrating ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● ● ● ● ● ● ● ● ● The ADS850 is a high dynamic range, 14-bit Analog-to-Digital Converter (ADC) that utilizes a fully differential input, allowing for either single-ended or differential input interface over varying input spans.
PAGE 2
ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) +VS ....................................................................................................... +6V Analog Input ........................................................... (–0.3V) to (+VS +0.3V) Logic Input ............................................................. (–0.3V) to (+VS +0.3V) Case Temperature ......................................................................... +100°C Junction Temperature .......................
PAGE 3
ELECTRICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, specified differential input range = 1.5V to 3.5V, internal reference input, sampling rate = 10MSPS after calibration, and VREF = 2V, unless otherwise specified.
PAGE 4
PIN CONFIGURATION IN GND IN GND CBP1 GND REFT CM REFB GND CBP2 TQFP GND Top View 48 47 46 45 44 43 42 41 40 39 38 37 +VS 1 36 +VS +VS 2 35 GND +VS 3 34 VREF +VS 4 33 SEL GND 5 32 GND CLK 6 NC 7 30 BTC MEM_RST 8 29 PD CAL 9 28 OE 31 GND ADS850Y OVR 10 27 GND CAL_BUSY 11 26 VDRV B4 B5 B6 B7 19 20 21 22 23 24 B13 18 B12 17 B11 16 B10 15 B9 14 B8 13 B3 25 B14 (LSB) B2 B1 (MSB) 12 PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12
PAGE 5
TIMING DIAGRAMS N+2 N+1 Analog In N+4 N+3 N tD N+5 tL tCONV N+6 N+7 tH CLK 7 Clock Cycles t2 Data Out N–7 N–6 N–5 N–4 N–3 N–2 N–1 Data Invalid SYMBOL t CONV tL tH tD t1 t2 N t1 DESCRIPTION MIN Convert Clock Period Clock Pulse LOW Clock Pulse HIGH Aperture Delay Data Hold Time, CL = 0pF New Data Delay Time, CL = 15pF max 100 48 48 TYP MAX UNITS 100µs ns ns ns ns ns ns t CONV /2 t CONV /2 2 3.9 12 TIMING DIAGRAM 1. Pipeline Delay Timing.
PAGE 6
TYPICAL CHARACTERISTICS At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, differential internal reference input and sampling rate = 10MSPS after calibration, VREF = 2V, –1dB input, unless otherwise specified. SPECTRAL PERFORMANCE (2Vp-p, Differential, fIN = 4.8MHz) SPECTRAL PERFORMANCE (4Vp-p, Differential, fIN = 4.8MHz) 0 0 SFDR = 89dBFS SNR = 76dBFS –10 –30 Amplitude (dB) Amplitude (dB) –30 –50 –70 –110 –110 –130 0.5 1 1.5 2 2.5 3 3.5 4 4.
PAGE 7
TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, differential internal reference input and sampling rate = 10MSPS after calibration, VREF = 2V, –1dB input, unless otherwise specified. DIFFERENTIAL LINEARITY ERROR INTEGRAL LINEARITY ERROR 1 4 fIN = 4.8MHz 3 0.5 2 0.25 1 ILE (LSB) DLE (LSB) fIN = 4.8MHz 0.75 0 –0.25 0 –1 –0.5 –2 –0.
PAGE 8
TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, differential internal reference input and sampling rate = 10MSPS after calibration, VREF = 2V, –1dB input, unless otherwise specified.
PAGE 9
TYPICAL CHARACTERISTICS (Cont.) At TA = full specified temperature range, VS = +5V, specified input range = 1.5V to 3.5V, differential internal reference input and sampling rate = 10MSPS after calibration, VREF = 2V, –1dB input, unless otherwise specified. SWEPT POWER 110 dBFS fIN = 4.
PAGE 10
+5V –5V 2Vp-p VIN +VIN 2kΩ RS 24.9Ω 0.1µF REFT (+3V) 2kΩ IN OPA642 0V 100pF –VIN RF 402Ω ADS850 2kΩ RG 402Ω +2.5VDC IN 0.1µF (+2V) REFB 2kΩ (+1V) VREF SEL FIGURE 1. AC-Coupled Input Configuration for 2Vp-p Input Swing and Common-Mode Voltage at +2.5V Derived from Internal Top and Bottom Reference. DC-COUPLED WITHOUT LEVEL SHIFT In some applications the analog input signal may already be biased at a level which complies with the selected input range and reference level of the ADS850.
PAGE 11
SINGLE-ENDED-TO-DIFFERENTIAL CONFIGURATION (TRANSFORMER COUPLED) REFERENCE OPERATION In order to select the best suited interface circuit for the ADS850, the performance requirements must be known. If an ac-coupled input is needed for a particular application, the next step is to determine the method of applying the signal; either single-ended or differentially.
PAGE 12
The top reference (REFT) and the bottom reference (REFB) are brought out mainly for external bypassing. For proper operation with all reference configurations, it is necessary to provide solid bypassing to the reference pins in order to keep the clock feedthrough to a minimum. Figure 5 shows the recommended reference decoupling configuration. down the internal reference.
PAGE 13
CLOCK INPUT REQUIREMENTS GROUNDING AND DECOUPLING Clock jitter is critical to the SNR performance of high-speed, high-resolution ADCs. It leads to aperture jitter (tA) which adds noise to the signal being converted. The ADS850 samples the input signal on the rising edge of the CLK input. Therefore, this edge should have the lowest possible jitter. The jitter noise contribution to total SNR is given by the following equation.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS850Y/250 TQFP PFB 48 250 177.8 16.4 9.6 9.6 1.5 12.0 16.0 Q2 ADS850Y/2K TQFP PFB 48 2000 330.0 16.8 9.6 9.6 1.5 12.0 16.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS850Y/250 TQFP PFB ADS850Y/2K TQFP PFB 48 250 210.0 185.0 35.0 48 2000 367.0 367.0 38.
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.