Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LQFP 64

CDAC1

CDAC2

SARRegister1/2

S/H

Comparator

CDAC3

CDAC4

SARRegister3/4

S/H

Comparator

CDAC5

CDAC6

SARRegister5/6

StringDAC

Clock

Generator

S/H

Comparator

Internal2.5V

Reference

I/O

Control

Logic

Config

CH_A0

CONVST_A

CH_A1

AGND

REFC_A

CH_B0

CONVST_B

CH_B1

AGND

REFC_B

CH_C0

CONVST_C

CH_C1

AGND

REFC_C

REF IO_

HVSS

AVDD

AGND

ADS8556

ADS8557

ADS8558

Buffer

HVDD

BVDD

BGND

HW/SW

REF /WR

STBY

RESET

RANGE/XCLK

BUSY/INT

DB[15:0]

WORD/BYTE

PAR/SER

CS/FS

ADS8556

ADS8557

ADS8558

www.ti.com

SBAS404B –OCTOBER 2006– REVISED JANUARY 2012

16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling

ANALOG-TO-DIGITAL CONVERTERS

Check for Samples: ADS8556, ADS8557, ADS8558

FEATURES

DESCRIPTION

The ADS8556/7/8 contain six low-power, 16-, 14-, or

• Family of 16-, 14-, 12-Bit, Pin- and

12-bit, successive approximation register (SAR)

Software-Compatible ADCs

based analog-to-digital converters (ADCs) with true

• Six SAR ADCs Grouped in Three Pairs

bipolar inputs. Each channel contains a

• Maximum Data Rate Per Channel with Internal

sample-and-hold circuit that allows simultaneous

high-speed multi-channel signal acquisition.

Conversion Clock and Reference:

ADS8556: 630kSPS (PAR) or 450kSPS (SER)

The ADS8556/7/8 support data rates of up to

ADS8557: 670kSPS (PAR) or 470kSPS (SER)

730kSPS in parallel interface mode or up to 500kSPS

ADS8558: 730kSPS (PAR) or 500kSPS (SER)

if the serial interface is used. The bus width of the

parallel interface can be set to eight or 16 bits. In

• Maximum Data Rate with External Conversion

serial mode, up to three output channels can be

Clock and Reference:

activated.

800kSPS (PAR) or 530kSPS (SER)

The ADS8556/7/8 is specified over the full industrial

• Pin-Selectable or Programmable Input Voltage

temperature range of –40°C to +125°C and is

Ranges: Up to ±12V

available in an LQFP-64 package.

• Excellent Signal-to-Noise Performance:

91.5dB (ADS8556)

85dB (ADS8557)

73.9dB (ADS8558)

• Programmable and Buffered Internal

Reference: 0.5V to 2.5V and 0.5V to 3.0V

• Comprehensive Power-Down Modes:

Deep Power-Down (Standby Mode)

Partial Power-Down

Auto-Nap Power-Down

• Selectable Parallel or Serial Interface

• Operating Temperature Range:

–40°C to +125°C

• LQFP-64 Package

APPLICATIONS

• Power Quality Measurement

• Protection Relays

• Multi-Axis Motor Control

• Programmable Logic Controllers

• Industrial Data Acquisition

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (42 pages)

PAGE 1
ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com 16-, 14-, 12-Bit, Six-Channel, Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS Check for Samples: ADS8556, ADS8557, ADS8558 FEATURES DESCRIPTION • The ADS8556/7/8 contain six low-power, 16-, 14-, or 12-bit, successive approximation register (SAR) based analog-to-digital converters (ADCs) with true bipolar inputs.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT 4.5 5 5.5 V Low-voltage levels 2.7 3.0 3.6 V 5V logic levels 4.5 5 5.5 V Supply voltage, AVDD to AGND Supply voltage, BVDD to BGND Input supply voltage, HVDD to AGND Input supply voltage, HVSS to AGND Range 1 (±2 × VREF) 2 × VREF 16.5 V Range 2 (±4 × VREF) 4 × VREF 16.5 V Range 1 (±2 × VREF) –16.5 –2 × VREF V Range 2 (±4 × VREF) –16.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8556 Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5V, BVDD = 2.7V to 5.5V, HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = 630kSPS in parallel mode or 450kSPS in serial mode, unless otherwise noted.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8557 Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V, HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = 670kSPS in parallel mode or 470kSPS in serial mode, unless otherwise noted.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: ADS8558 Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5V, BVDD = 2.7V to 5.5V, HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = 730kSPS in parallel mode or 500kSPS in serial mode, unless otherwise noted.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V, HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL (continued) Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V, HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL (continued) Over recommended operating free-air temperature range of –40°C to +125°C, AVDD = 4.5V to 5.5V, BVDD = 2.7V to 5.5V, HVDD = 10V to 15V, HVSS = –15V to –10V, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com TERMINAL FUNCTIONS DESCRIPTION NAME DB14/REFBUFEN PIN # 1 TYPE (1) DIO/DI PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) Data bit 14 input/output Output is '0' for the ADS8557/8 Hardware mode (HW/SW = 0): Reference buffers enable input. When low, all reference buffers are enabled (mandatory if internal reference is used). When high, all reference buffers are disabled.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com TERMINAL FUNCTIONS (continued) DESCRIPTION NAME DB0/SEL_A PIN # 17 TYPE (1) DIO/DI BUSY/INT 18 DO CS/FS 19 DI/DI RD 20 DI CONVST_C 21 DI PARALLEL INTERFACE (PAR/SER = 0) Word mode (WORD/BYTE = 0): Data bit 0 (LSB) input/output Byte mode (WORD/BYTE = 1): Connect to BGND or BVDD SERIAL INTERFACE (PAR/SER = 1) Select SDO_A input. When high, SDO_A is active. When low, SDO_A is disabled. Should always be high.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com TERMINAL FUNCTIONS (continued) DESCRIPTION NAME PIN # TYPE (1) PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1) HVDD 31 P Positive supply voltage for the analog inputs (5V to 16.5V). Decouple with a 100nF ceramic capacitor to AGND placed next to the device and a 10μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor.
PAGE 14
ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com TIMING CHARACTERISTICS XCLK (C11 = 1) tS3 tS3 t1 CONVST_x tACQ tCONV tD1 BUSY (C20 = C21 = 0) t3 t2 FS tSCLK 32 1 SCLK tD4 tD3 tD2 ADS8556 SDO_x CH_x0 MSB tH2 CH_x1 D3 tS1 SDI or DCIN_x Don’t Care D31 D3 CH_x1 D2 tH1 CH_x1 D1 CH_x1 LSB D2 D1 D0 Don’t Care Figure 2.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com t1 CONVST_A CONVST_B CONVST_C tCONV tACQ tD1 BUSY (C20 = C21 = 0) t3 t2 CS t4 t6 t5 t7 RD tD5 CH A0 DB[15:0] CH A1 CH B0 tH3 CH C0 CH B1 CH C1 Figure 3. Parallel Read Access Timing Diagram Parallel Interface Timing Requirements (Read Access) (1) Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless otherwise noted.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com CS t9 t10 t11 t8 WR tS2 tH4 C [31:16] DB[15:0] C [15:0] Don’t Care Word Mode (WORD/BYTE = 0) C [31:24] C [15:8] C [23:16] C [7:0] Byte Mode (WORD/BYTE = 1) Figure 4. Parallel Write Access Timing Diagram Parallel Interface Timing Requirements (Write Access) (1) Over recommended operating free-air temperature range at –40°C to +125°C, AVDD = 5V, and BVDD = 2.7V to 5.5V, unless otherwise noted.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. INL vs CODE (ADS8556 ±10VIN Range) 3.0 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -3.0 0 1.5 8190 16380 24570 32760 40950 49140 57330 65520 8190 16380 24570 32760 40950 49140 57330 65520 Code Figure 5. Figure 6.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. DNL vs CODE (ADS8557 ±10VIN Range) 1.0 AVDD = BVDD = 5V HVSS = -15V HVDD = 15V fDATA = Max Internal Reference 0.8 0.6 0.4 Differential Nonlinearity (LSB) Differential Nonlinearity (LSB) 1.0 DNL vs CODE (ADS8557 ±5VIN Range) 0.2 0 -0.2 -0.4 -0.6 -0.8 0.6 0.4 0.2 0 -0.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. PSRR vs AVDD NOISE FREQUENCY CONVERSION TIME vs TEMPERATURE 1.40 CSUPPLY = 100nF on AVDD 1.35 -40 Conversion Time (ms) Power-Supply Rejection Ratio (dB) -30 -50 -60 -70 1.30 1.25 ADS8556 1.20 ADS8557 1.15 1.10 1.05 ADS8558 1.00 -80 0.95 -90 0.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. INTERNAL REFERENCE VOLTAGE vs TEMPERATURE (3.0V Mode) ANALOG SUPPLY CURRENT vs TEMPERATURE 3.005 3.004 3.003 IAVDD (mA) VREF (V) 3.002 3.001 3.000 2.999 2.998 2.997 2.996 2.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At +25°C, over entire supply voltage range, VREF = 2.5V (internal), and fDATA = maximum, unless otherwise noted. ADS8556 INPUT SUPPLY CURRENT vs DATA RATE 3.6 IHVSS 3.3 3.0 IHVSS (A-NAP) IHVxx (mA) 2.7 2.4 2.1 IHVDD (A-NAP) 1.8 1.5 IHVDD 1.2 0.9 HVSS = -15V HVDD = 15V Range = ±4 ´ VREF 0.6 0.3 0 0 90 180 270 360 450 540 630 Data Rate (kSPS) Figure 35.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com GENERAL DESCRIPTION The ADS8556/7/8 series include six 16-, 14-, and 12-bit analog-to-digital converters (ADCs) respectively that operate based on the successive approximation register (SAR) principle. The architecture is designed on the charge redistribution principle, which inherently includes a sample-and-hold function. The six analog inputs are grouped into three channel pairs.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com Conversion Clock The device uses either an internally-generated or an external (XCLK) conversion clock signal (in software mode only). In default mode, the device generates an internal clock. When the CLKSEL bit is set high (bit C11 in the CR), an external conversion clock of up to 20MHz (max) can be applied on pin 27. In both cases, 18.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com BUSY/INT The BUSY signal indicates if a conversion is in progress. It goes high with a rising edge of any CONVST_x signal and goes low when the output data of the last channel pair are available in the respective output register. The readout of the data can be initiated immediately after the falling edge of BUSY.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 DIGITAL This section describes the digital control and the timing of the device in detail. Device Configuration Depending on the desired mode of operation, the ADS8556/7/8 can be configured using the external pins and/or the control register ( CR), as shown in Table 2. Parallel Interface To use the device with the parallel interface, the PAR/SER pin should be held low.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com CONVST_A CONVST_B CONVST_C BUSY (C20 = C21 = 0) 48 SCLKs SEL_A = SEL_B = 1, SEL_C = 0 FS SDO_A CHA0 CHA1 CHC0 SDO_B CHB0 CHB1 CHC1 SEL_A = 1, SEL_B = SEL_C = 0 96 SCLKs FS SDO_A CHA0 CHA1 CHB0 CHB1 CHC0 CHC1 Figure 37.
PAGE 28
ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com RESET (or Power-Up) BUSY (C20 = C21 = 0) PAR/SER = 1 FS C[31:0] Initialization Data SDI Continuous Update Continuous Update C [31:24] C [31:24] PAR/SER = 0; WORD/BYTE = 0 CS WR Initialization Data DB[15:0] C [31:16] Update C [15:0] C [31:24] C [15:0] PAR/SER = 0; WORD/BYTE = 1 WR Initialization Data DB[15:8] C [31:24] C [23:16] C [15:8] Update C [31:24] C [7:0] C [23:16] Figure 38.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com Table 3.
PAGE 30
ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com Daisy-Chain Mode (in Serial Mode Only) XCLK Sequential Mode (in Software Mode with External Conversion clock Only) The three channel pairs of the ADS8556/7/8 can be run in sequential mode, with the corresponding CONVST_x signals interleaved, when an external clock is used. To activate the device in sequential mode, CR bits C11 (CLKSEL) and C23 (SEQ) must be asserted.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com The entire device, except the digital interface, can be powered down by pulling the STBY pin low (pin 24). As the digital interface section remains active, data can be retrieved while in stand-by mode. To power the part on again, the STBY pin must be brought high. The device is ready to start a new conversion after 10ms required to activate and settle the internal circuitry.
PAGE 33
ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com Table 5.
PAGE 34
ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com ADS8556/7/8 Top View To AVDD To AVDD To DUT AVDD Source 10 mF AVDD 51 0.1mF AGND 54 0.47mF AGND 56 10mF AGND 58 10mF AGND 61 AGND 62 10mF 1 48 2 AVDD 3 AVDD 4 45 5 AGND 6 AGND 7 42 BGND AVDD BVDD AVDD 10 39 14 AVDD 15 AVDD 16 33 17 18 19 20 21 22 23 24 0.1mF LEGEND To AVDD 27 28 29 0.1 mF To AVDD 0.1 mF 0.1 mF To AVDD 0.1 mF 0.1 mF To AVDD 0.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com APPLICATION INFORMATION The actual values of the resistors and capacitors depend on the bandwidth and performance requirements of the application. For highest data rate, it is recommended to use a filter capacitor value of 1nF and a series resistor of 22Ω to fulfill the settling requirements to an accuracy level of 16 bits within the acquisition time of 280ns.
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ADS8556 ADS8557 ADS8558 SBAS404B – OCTOBER 2006 – REVISED JANUARY 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (August 2009) to Revision B Page • Updated Figure 2 ................................................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 38
PACKAGE OPTION ADDENDUM www.ti.com 30-Nov-2011 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8556IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 ADS8557IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.0 Q2 ADS8558IPMR LQFP PM 64 1000 330.0 24.4 13.0 13.0 2.1 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8556IPMR LQFP PM 64 1000 367.0 367.0 45.0 ADS8557IPMR LQFP PM 64 1000 367.0 367.0 45.0 ADS8558IPMR LQFP PM 64 1000 367.0 367.0 45.
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MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.