Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal SSOP 28

Pipeline

A/D

Internal

Reference

Timing

Circuitry

Error

Correction

3-State

Outputs

T/H

8-Bit

Digital

Data

CLK

ADS930

OEPwrdn1V

REF

LnByCMLpBy

(Opt.)

FEATURES

● +3V TO +5V SUPPLY OPERATION

● INTERNAL REFERENCE

● SINGLE-ENDED INPUT RANGE: 1V to 2V

● LOW POWER: 66mW at +3V

● HIGH SNR: 46dB

● LOW DNL: 0.4LSB

● SSOP-28 PACKAGE

DESCRIPTION

The ADS930 is a high speed pipelined Analog-to-Digital

Converter (ADC) specified to operate from nominal +3V or

+5V power supplies with tolerances of up to 10%. This

complete converter includes a high bandwidth track/hold, a

8-bit quantizer and an internal reference.

The ADS930 employs digital error correction techniques to

provide excellent differential linearity for demanding im-

aging applications. Its low distortion and high SNR give the

extra margin needed for telecommunications, video and

test instrumentation applications.

This high performance ADC is specified for performance at

a 30MHz sampling rate. The ADS930 is available in a

SSOP-28 package.

8-Bit, 30MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

APPLICATIONS

● BATTERY POWERED EQUIPMENT

● CAMCORDERS

● PORTABLE TEST EQUIPMENT

● COMPUTER SCANNERS

● COMMUNICATIONS

ADS930E

ADS930

SBAS059A – MARCH 2001

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (15 pages)

PAGE 1
ADS930 ADS 930 E SBAS059A – MARCH 2001 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER TM FEATURES ● ● ● ● ● ● ● DESCRIPTION +3V TO +5V SUPPLY OPERATION INTERNAL REFERENCE SINGLE-ENDED INPUT RANGE: 1V to 2V LOW POWER: 66mW at +3V HIGH SNR: 46dB LOW DNL: 0.4LSB SSOP-28 PACKAGE The ADS930 is a high speed pipelined Analog-to-Digital Converter (ADC) specified to operate from nominal +3V or +5V power supplies with tolerances of up to 10%.
PAGE 2
ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY +VS ....................................................................................................... +6V Analog Input ............................................................................... +VS +0.3V Logic Input ................................................................................. +VS +0.3V Case Temperature ......................................................................... +100°C Junction Temperature ...........
PAGE 3
ELECTRICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified.
PAGE 4
PIN CONFIGURATION PIN DESCRIPTIONS Top View SSOP +VS 1 28 +VS LVDD 2 27 +IN NC 3 26 CM NC 4 25 LnBy LSB Bit 8 5 24 IN Bit 7 6 23 1VREF Bit 6 7 22 NC Bit 5 8 21 LpBy Bit 4 9 20 GND Bit 3 10 19 GND Bit 2 11 18 +VS MSB Bit 1 12 17 Pwrdn GND 13 16 OE GND 14 15 CLK ADS930 PIN DESIGNATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 +VS LVDD NC NC Bit 8 (LSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1(MSB) GND GND CLK OE Pwrdn
PAGE 5
TYPICAL CHARACTERISTICS At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified. SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE 0 0 fIN = 500kHz fIN = 3.58MHz –20 Amplitude (dB) Amplitude (dB) –20 –40 –60 –40 –60 –80 –80 –100 –100 0 5 10 0 15 5 10 SPECTRAL PERFORMANCE TWO-TONE INTERMODULATION 0 0 fIN = 12MHz f1 = 3.5MHz at –7dBFS f2 = 3.4MHz at –7dBFS 2f1 –f2 = 54.7dBFS 2f2 –f1 = 54.
PAGE 6
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified. SWEPT POWER SFDR INTEGRAL LINEARITY ERROR 100 4.0 fIN = 500kHz SFDR (dBFS, dBc) 2.0 ILE (LSB) dBFS 80 0 –2.0 60 40 20 dBc –4.
PAGE 7
TYPICAL CHARACTERISTICS (Cont.) At TA = +25°C, VS = +3V, Single-ended Input and Sampling Rate = 30MHz, unless otherwise specified. SIGNAL-TO-NOISE RATIO vs TEMPERATURE POWER DISSIPATION vs TEMPERATURE 48 SNR (dB) 47 Power Dissipation (mW) 69 fIN = 12MHz 46 fIN = 500kHz 45 44 –50 68 67 66 65 –25 0 25 50 75 100 –50 –25 0 Temperature (°C) GAIN ERROR vs TEMPERATURE 50 75 100 OFFSET ERROR vs TEMPERATURE 6.5 7 6.0 6 Offset Error (mV) Gain (%FSR) 25 Temperature (°C) 5.5 5.
PAGE 8
THEORY OF OPERATION Op Amp Bias The ADS930 is a high speed sampling ADC that utilizes a pipeline architecture. The fully differential topology and digital error correction guarantee 8-bit resolution. The track/ hold circuit is shown in Figure 1. The switches are controlled by an internal clock which has a non-overlapping two phase signal, φ1 and φ2. At the sampling time the input signal is sampled on the bottom plates of the input capacitors.
PAGE 9
The pipelined quantizer architecture has 7 stages with each stage containing a two-bit quantizer and a two bit Digitalto-Analog Converter (DAC), as shown in Figure 2. Each two-bit quantizer stage converts on the edge of the subclock, which is the same frequency of the externally applied clock. The output of each quantizer is fed into its own delay line to time-align it with the data created from the subsequent quantizer stages.
PAGE 10
DC-COUPLED INTERFACE CIRCUIT Figure 5 illustrates an example of a DC-coupled interface circuit using one high-speed op amp to level-shift the groundreferenced input signal. This serves to condition it for the input requirements of the ADS930. With a +3V supply the input signal swings 1Vp-p centered around a typical common-mode voltage of +1.5V. This voltage can be derived from the internal bottom reference (REFB) and then fed back through a resistor divider (R1, R2) to level-shift the driving op amp (A1).
PAGE 11
are recommended to meet the rated performance specifications. However, the ADS930 performance is tolerant to duty cycle variations of as much as ±10%, which should not affect the performance. For applications operating with input frequencies up to Nyquist (fCLK/2) or undersampling applications, special considerations must be made to provide a clock with very low jitter. Clock jitter leads to aperture jitter (tA) which can be the ultimate limitation in achieving good SNR performance.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS930E/1K Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.2 10.5 2.5 12.0 16.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS930E/1K SSOP DB 28 1000 346.0 346.0 33.
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.