Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 16 Bit LQFP-128

AFE0064

www.ti.com

........................................................................................................................................................................................ SLAS672 –SEPTEMBER 2009

64 Channel Analog Front End for Digital X-Ray Detector

Check for Samples :AFE0064

FEATURES

DESCRIPTION

• 64 Channels

• 28.32 µSec Min Scan Time (including

The AFE0064 is a 64 channel analog front end

designed to suit the requirements of flat panel

integration and data transfer for all 64

detector based digital X-ray systems.

channels)

• 7.5 MHz Max Data Transfer Rate

The device includes 64 integrators, a PGA for full

scale charge level selection, correlated double

• Noise 824 e-RMS with 30 pF Sensor Capacitor

sampler, 64 as to 2 multiplexer, and two differential

in 1.2 pC Range

output drivers.

• Integral Nonlinearity: ±0.006% of FSR

Hardware selectable Integration polarity allows

• Eight Adjustable Full Scale Ranges (0.13 pC

integration of a positive or negative charge and

min to 9.5 pC max)

provides more flexibility in system design. In addition,

• Built in CDS (signal sample – offset sample)

the device features TFT (Thin Film Transistor from

Flat Panel Detector) charge injection compensation.

• Selectable Integration Up/Down Mode

This feature helps maximize the usable signal charge

• Low Power: 175 mW

range of the device.

• NAP Mode: 49.5 mW

The nap feature enables substantial power saving.

• 14 mm × 14 mm 128 Pin TQFP Package

This is especially useful for power saving during long

X-ray exposure periods.

APPLICATIONS

The AFE0064 is available in a 128 pin TQFP

• Digital Radiography

package.

• CT Scanners

• Baggage Scanners

• Infrared Spectroscopy

ORDERING INFORMATION

(1)

INTEGRAL MIN SCAN TRANSPORT

POWER NUMBER OF PACKAGE PACKAGE TEMPERATURE ORDERING

MODEL LINEARITY TIME MEDIA

DISSIPATION CHANNELS TYPE DESIGNATOR RANGE INFORMATION

% of FS (µSec) QUANTITY

AFE0064IPBK 90(5+1)

AFE0064 0.006 175 mW 28.32 64 TQFP PBK –40 to 85°C

AFE0064IPBKR 1000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 64 Channel Analog Front End for Digital X-Ray Detector Check for Samples :AFE0064 FEATURES 1 • • DESCRIPTION 64 Channels 28.32 µSec Min Scan Time (including integration and data transfer for all 64 channels) 7.
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE / UNIT IN to VSS –0.3 V to +VDD + 0.3 V VDD to AGND –0.3 V to 5 V Digital input voltage to GND –0.3 V to (+VDD + 0.3 V) Digital output to GND –0.3 V to (+VDD + 0.
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com SPECIFICATIONS (continued) TA = 25 to 85°C, +VDD = 3.3 V, fCLK = 15 MHz for sequential mode and 3.75 MHz for simultaneous mode, scan time = 28.
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 TIMING REQUIREMENTS TA = 0 to 85°C, +VDD = 3.3 V PARAMETER MIN TYP MAX UNIT (1) µSec SAMPLING AND CONVERSION RELATED t-scan Scan time, See Figure 1, Figure 7 28.
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.
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AFE0064 www.ti.com ........................................................................................................................................................................................
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 t- Scan t1 IRST t7 t9 SHR t4 INTG t3 TFT ON (t5) SHS t1 ~0.5 uSec t1 t8 t6 STI t2 CLK DATA READ EOC Figure 2. Integration and Data Read As shown in Figure 2, the device performs two functions, ‘Integration’ and ‘Data Read’ during each scan (indicated by 't-Scan').
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com In this period, the reset sample capacitor is tracking the integrator output voltage. On the 64th CLK falling edge, the filter bypass switch is opened. This kicks in the low pass filter. The filter has a fixed time constant of 1 µSec (160 kHz BW).
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 As explained before the device samples the integrator output twice, Reset sample ( SHR) and Signal sample (SHS).
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com A high pulse on STI activates the data read function and resets the channel counter to zero. As shown in Figure 5, the device outputs the analog voltage from channel 63 on the first rising edge of CLK after STI falling edge.
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 t - Scan t1 IRST t9 SHR t4 INTG t3 SHS t1 TFT ON (t5) t1 ~0.5 mSec t6 t8 STI t2 CLK WAIT Additional 133 clocks DATA READ EOC Figure 7.
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 Pin 56, 57 V(EXT_C) S1 C1 = 0.857 pC S1 Compensation scheme Pixel cap TFT Switch Ch-n IN-n V(EXT_C) IRST SHR SHS TFT Switch on DF-SM INTG TFT charge injection Compensation charge C1 charge injection = (V at Pins 56,57 – V at ‘EXT_C’)* 0.
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com As shown in Figure 9, the TFT injects a charge during turn on and an opposite polarity charge during turn off. (For this example the injected charge during TFT turn on is positive.) This drives the integrator output –ve.
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 IRST SHR SHS TFT Switch on DF-SM INTG +ve charge (Integrator down) Compensation charge C1 charge injection = (V at Pins 56,57 – Voltage at ‘ECT_C’)* 0.
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS HISTOGRAM OF OUTPUT OFFSET DRIFT WITH +VDD SUPPLY VARIATION HISTOGRAM OF OUTPUT OFFSET DRIFT WITH FREE-AIR TEMPERATURE 900 450 TA = 45°C, VDD = 3.2 V to 3.6 V, Range = 9.6 pC 800 400 350 Count of Channels Count of Channels 700 VDD = 3.2 V to 3.
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 TYPICAL CHARACTERISTICS (continued) GAIN ERROR vs RANGE CHANNEL TO CHANNEL CROSSTALK vs CHANNEL NUMBER 14 0.08 TA = 45°C, VDD = 3.4 V 0.07 Channel to Channel Crosstalk - %FS Gain Error - %Full Scale 12 10 8 6 4 2 Stimulus 90% of FSR, TA = 45°C, VDD = 3.
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) COUNT OF CHANNELS vs LEAKAGE CURRENT DRIFT WITH FREE-AIR TEMPERATURE NOISE vs CHANNEL NUMBER IN RANGE 0 720 450 400 VDD = 3.4 V, Range =2.4 pC 700 680 Noise - in Electrons Channel Count 350 300 250 200 150 640 620 TA = 45°C, VDD = 3.
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 TYPICAL CHARACTERISTICS (continued) NOISE vs CHANNEL NUMBER IN RANGE 3 NOISE vs CHANNEL NUMBER IN RANGE 4 860 1040 840 1020 Noise - in Electrons Noise - in Electrons 820 800 780 760 TA = 45°C, VDD = 3.4 V, Range = 1.
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) NOISE vs CHANNEL NUMBER IN RANGE 7 NOISE vs INTEGRATION TIME 1400 2700 TA = 45°C, VDD = 3.4 V, 2650 Range = 9.6 PC, Bus Cap = 24 pF 1200 TA = 45°C, VDD = 3.4 V, Range = 1.
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 APPLICATION INFORMATION INTERFACING FLAT PANEL DETECTOR (FPD) The following figure shows interfacing a flat panel detector to an AFE0064. The flat panel detector is a matrix of pixels. Each pixel consists of a photo diode and Thin Film Transistor switch.
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AFE0064 SLAS672 – SEPTEMBER 2009 ........................................................................................................................................................................................ www.ti.com STO #1 STI #2 Contact TI sales for suitable ADC. Figure 32. Typical Schematic Showing Four Channel ADC Interface with Two AFEs RESETTING THE FPD PANEL It is possible to reset the photo diodes using IRST.
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AFE0064 www.ti.com ........................................................................................................................................................................................ SLAS672 – SEPTEMBER 2009 AFE TRANSFER CHARACTERISTICS 3.5 Ideal P 3 Output Voltage 2.5 Practical P 2 1.5 1 Practical M 0.5 Ideal M 0 0 20 40 60 80 100 % input charge 120 140 160 The plot above shows AFE transfer characteristics in integrator down mode.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device AFE0064IPBKR Package Package Pins Type Drawing LQFP PBK 128 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 17.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 17.0 2.1 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AFE0064IPBKR LQFP PBK 128 1000 367.0 367.0 45.
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