Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 10 Bit VQFN 48

Table Of Contents

DVDD

DGND

AGND1

AVDD1

AGND2

AVDD2

SCLK

DAC

Tx_FLAG

Rx_FLAG

INT

REF1

REF2

ZC_OUT2

ZC_OUT1

ZC_IN1

ZC_IN2

PA_ISET

PA_VS

PA_GND

TSENSE

PA_OUT

E_Rx_IN

E_Rx_OUT

E_Tx_CLK

E_Tx_IN

E_Tx_OUT

Rx_PGA1_IN

Rx_PGA1_OUT

Rx_F_IN

Rx_C1

Rx_C2

Rx_F_OUT

Tx_PGA_IN

TX_PGA_OUT

Tx_F_IN1

Tx_F_IN2

Tx_F_OUT

PA_IN

Rx_PGA2_OUT

Rx_PGA2_IN

Bias

ZC2

ZC1

Power

Amplifier

Digital Interface

(SPI)

Control

Digital-to-Analog

Converter

TxPGA

RxPGA_1

RxPGA_2

Tx Filter

Rx Filter

Two-Wire Rx/Tx

AFE031

www.ti.com

SBOS531D –AUGUST 2010–REVISED MAY 2012

Powerline Communications

Analog Front-End

Check for Samples: AFE031

FEATURES

DESCRIPTION

The AFE031 is a low-cost, integrated, powerline

234

• Integrated Powerline Driver with Thermal and

communications (PLC) analog front-end (AFE) device

Overcurrent Protection

that is capable of capacitive- or transformer-coupled

• Conforms to EN50065-1

connections to the powerline while under the control

• PRIME Certified

of a DSP or microcontroller. It is ideal for driving low-

impedance lines that require up to 1.5 A into reactive

• Large Output Swing: 12 V

at 1.5 A

loads. The integrated receiver is able to detect

(15-V Supply)

signals down to 20 μV

RMS

and is capable of a wide

• Low Power Consumption:

range of gain options to adapt to varying input signal

15 mW (Receive Mode)

conditions. This monolithic integrated circuit provides

high reliability in demanding powerline

• Programmable Tx and Rx Filters

communications applications.

• Supports EN50065 CENELEC Bands A, B, C, D

The AFE031 transmit power amplifier operates from a

• Supports FSK, S-FSK, and OFDM

single supply in the range of 7 V to 24 V. At

• Supports PRIME, G3, IEC 61334

maximum output current, a wide output swing

• Receive Sensitivity: 20 μV

RMS

, Typical

provides a 12-V

OUT

= 1.5 A) capability with a

nominal 15-V supply. The analog and digital signal

• Programmable Tx and Rx Gain Control

processing circuitry operates from a single 3.3-V

• Four-Wire Serial Peripheral Interface

power supply.

• Two Integrated Zero Crossing Detectors

The AFE031 is internally protected against

• Two-Wire Transceiver Buffer

overtemperature and short-circuit conditions. It also

• 48-Pin QFN PowerPAD™ Package

provides an adjustable current limit. An interrupt

output is provided that indicates both current limit and

• Extended Junction Temperature Range:

thermal limit. There is also a shutdown pin that can

–40°C to +125°C

be used to quickly put the device into its lowest

power state. Through the four-wire serial peripheral

APPLICATIONS

interface, or SPI™, each functional block can be

• eMetering

enabled or disabled to optimize power dissipation.

• Lighting

The AFE031 is housed in a thermally-enhanced,

• Solar

surface-mount PowerPAD package (QFN-48).

Operation is specified over the extended industrial

• Pilot Wire

junction temperature range of –40°C to +125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD, C2000 are trademarks of Texas Instruments.

3SPI is a trademark of Motorola, Inc.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (57 pages)

PAGE 1
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 Powerline Communications Analog Front-End Check for Samples: AFE031 FEATURES DESCRIPTION • Integrated Powerline Driver with Thermal and Overcurrent Protection • Conforms to EN50065-1 • PRIME Certified • Large Output Swing: 12 VPP at 1.
PAGE 2
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS: Transmitter (Tx) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. AFE031 PARAMETER CONDITIONS MIN TYP MAX UNIT Tx_DAC Output range GND + 0.1 Resolution AVDD – 0.1 V 3.2 mV Second harmonic distortion –73 dB Third harmonic distortion –56 dB Fourth harmonic distortion –94 dB 1.5 MSPS Total harmonic distortion at 62.
PAGE 4
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: Transmitter (Tx) (continued) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. AFE031 PARAMETER CONDITIONS MIN TYP MAX UNIT Tx_FILTER Input Input voltage range Input resistance (Tx_F_IN1 and Tx_F_IN2) GND – 0.1 RI AVDD + 0.
PAGE 5
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS: Power Amplifier (PA) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. AFE031 PARAMETER CONDITIONS MIN TYP MAX UNIT Input Input voltage range Input resistance PA_VS + 0.1 GND – 0.
PAGE 6
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: Receiver (Rx) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. AFE031 PARAMETER CONDITIONS MIN TYP MAX UNIT Rx PGA1 Input Input voltage range Input resistance RI 10 VPP G = 2 V/V 10 kΩ G = 1 V/V 15 kΩ G = 0.5 V/V 20 kΩ G = 0.25 V/V 24 kΩ G = 2 V/V 6 MHz Frequency Response Bandwidth BW G = 1 V/V 10 MHz G = 0.
PAGE 7
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS: Receiver (Rx) (continued) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. AFE031 PARAMETER CONDITIONS MIN TYP MAX UNIT Rx PGA2 Input Input voltage range Input impedance GND – 0.1 AVDD + 0.1 V G = 64 V/V 1.7 kΩ G = 16 V/V 6.3 kΩ G = 4 V/V 21 kΩ G = 1 V/V 53 kΩ G = 64 V/V 300 kHz G = 16 V/V 800 kHz G = 4 V/V 1.
PAGE 8
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: Digital At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. AFE031 PARAMETER CONDITIONS MIN TYP MAX UNIT Digital Inputs (SCLK, DIN, CS, DAC, SD) 0 ≤ VIN ≤ DVDD Leakage input current –1 0.01 1 μA Input logic levels High-level input voltage VIH Low-level input voltage VIL SD pin high 0.7 • DVDD SD > 0.7 • DVDD SD pin low V 0.
PAGE 9
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 ELECTRICAL CHARACTERISTICS: Two-Wire Interface At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. AFE031 PARAMETER CONDITIONS MIN TYP MAX UNIT TWO-WIRE TRANSMITTER Frequency range (1) 50 Leakage input current (E_Tx_In, E_Tx_Clk) 0 ≤ VIN ≤ DVDD –1 kHz 0.01 1 μA Input logic levels (E_Tx_In, E_Tx_Clk) High-level input voltage VIH Low-level input voltage VIL 0.
PAGE 10
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: Power Supply At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. AFE031 PARAMETER CONDITIONS MIN TYP MAX UNIT Operating Supply Range Power amplifier supply voltage PA_VS +7 +24 V Digital supply voltage DVDD +3.0 +3.6 V Analog supply voltage AVDD +3.0 +3.
PAGE 11
AFE031 www.ti.
PAGE 12
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com tCSH CS tCSSC tSCCS tHI tCS1 tCS0 tLO SCLK tSU tHD 1/fSCLK DIN tSOZ tDO Hi-Z Hi-Z DOUT Figure 2. SPI Mode 1,1 CS W0 SDI SDO W1 XX W3 W2 XX XX XX W - Command of Write Register N XX - Don’t care; undefined. Figure 3. Write Operation in Stand-Alone Mode CS SDI SDO R0 R1 D0 XX R2 D1 R3 D2 Any Command D3 R - Command of Read Register N Read D - Data from Register N XX - Don’t care; undefined. Figure 4.
PAGE 13
AFE031 www.ti.
PAGE 14
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com PIN DESCRIPTIONS AFE031 PIN NO.
PAGE 15
AFE031 www.ti.
PAGE 16
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. Tx Filter GAIN vs FREQUENCY Rx Filter GAIN vs FREQUENCY 20 20 CENELEC A CENELEC B,C,D 0 0 −10 −10 −20 −30 −20 −30 −40 −40 −50 −50 −60 10k 100k Frequency (Hz) CENELEC A CENELEC B,C,D 10 Gain (dB) Gain (dB) 10 −60 10k 1M 100k Frequency (Hz) G001 Figure 5.
PAGE 17
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. Rx PGA2 GAIN vs FREQUENCY TWO-WIRE RECEIVER GAIN vs FREQUENCY 20 60 Gain = 64 V/V Gain = 16 V/V Gain = 4 V/V Gain = 1 V/V 50 40 0 20 Gain (dB) Gain (dB) 30 10 10 0 −10 −20 −10 −20 −30 −30 −40 10k 100k 1M Frequency (Hz) 10M −40 10k 100M 100k Frequency (Hz) G007 Figure 11.
PAGE 18
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. Rx PGA2 GAIN ERROR vs TEMPERATURE QUIESCENT SUPPLY CURRENT vs TEMPERATURE 0.4 60 0.3 Supply Current (mA) 0.2 Gain Error (%) PA Current (PA Enabled) AVDD Current (RX Mode) AVDD Current (TX Mode) 50 0.1 0 −0.1 −0.2 40 30 20 10 −0.3 −0.
PAGE 19
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) At TJ = +25°C, PA_VS = 16 V, VAVDD = VDVDD = 3.3 V, and 10 kΩ connected to PA_ISET (pin 46), unless otherwise noted. Rx PULSE RESPONSE 0.2 Rx Filter CENELEC A Rx Filter CENELEC B 0.15 Voltage (V) 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 0 10 µs/div (dB) G019 Figure 23.
PAGE 20
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com APPLICATION INFORMATION GENERAL DESCRIPTION The AFE031 is an integrated powerline communication analog front-end (AFE) device built from a variety of functional blocks that work in conjunction with a microcontroller. The AFE031 provides the interface between the microcontroller and a line coupling circuit. The AFE031 delivers high performance and is designed to work with a minimum number of external components.
PAGE 21
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 BLOCK DESCRIPTIONS PA Block The Power Amplifier (PA) block consists of a high slew rate, high-voltage, and high-current operational amplifier. The PA is configured with an inverting gain of 6.5 V/V, has a low-pass filter response, and maintains excellent linearity and low distortion. The PA is specified to operate from 7 V to 24 V and can deliver up to ±1.
PAGE 22
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com The external capacitor, CIN, introduces a single-pole, high-pass characteristic to the PA transfer function; combined with the inherent low-pass transfer function, this characteristic results in a passband response.
PAGE 23
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 The proper connections for the Tx signal path for DAC mode operation are shown in Figure 27. Operating in DAC mode results in the lowest distortion signal injected onto the ac mains. No additional external filtering components are required to meet CENELEC requirements for A, B, C or D bands when operating in DAC mode.
PAGE 24
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com Note (1) Inside the AFE031 MCU 43 kW Tx_F_IN1 PA_OUT1 GPIO PGA LPF Tx_F_IN2 PA GPIO PA_OUT2 43 kW Tx_F_OUT Tx_PGA_ Tx_PGA_ IN OUT PA_IN C C= 1 Note (2) 2·p·f·22 kW (1) When using both Tx Filter inputs, use 43-kΩ resistors to match the input resistance for best frequency response. (2) For capacitor value C, f is the desired lower cutoff frequency and 22 kΩ is the PA input resistance. Figure 29.
PAGE 25
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 Note (1) Inside the AFE031 MCU 43 kW Tx_F_IN1 PA_OUT1 GPIO Tx_F_IN2 PGA LPF PA GPIO PA_OUT2 43 kW Tx_F_OUT 510 W Tx_PGA_ Tx_PGA_ OUT IN PA_IN 510 W C C C C= 1 Note (3) 2·p·f·22 kW Note (2) (1) When using both Tx Filter inputs, use 43-kΩ resistors to match the input resistance for best frequency response. (2) Refer to Table 2.
PAGE 26
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com The Rx Filter is a very low noise, unity-gain, fourth-order low-pass filter. The Rx Filter cutoff frequency is selectable between CENELEC A or CENELEC B, C, and D modes. The Control1 Register bit location 3 setting (CA CBCD) determines the cutoff frequency. Setting Control1 Register bit location 3 to '0' selects the CENELEC A band; setting Control1 Register bit location 3 to '1' selects the CENELEC B, C, and D bands.
PAGE 27
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 The following steps can be used to quickly design the passive passband filter. (Note that these steps produce an approximate result.) 1. Choose the filter characteristic impedance, ZC: – For –6-db passband attenuation: R1 = R2 = ZC – For 0-db passband attenuation: R1 = ZC, R2 = 10 ● ZC 2.
PAGE 28
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com The Rx PGA1, Rx Filter, and Rx PGA2 components have all inputs and outputs externally available to provide maximum system design flexibility. Care should be taken when laying out the PCB traces from the inputs or outputs to avoid excessive capacitive loading. Keeping the PCB capacitance from the inputs to ground, or outputs to ground, below 100 pF is recommended.
PAGE 29
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 CS DAC DIN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SCLK Time NOTE: Dashed lines indicate optional additional clocks (data are ignored). Figure 35. Writing to the DAC Register Table 6 lists the DAC Register configurations. Table 6.
PAGE 30
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com REF1 and REF2 Blocks The REF1 and REF2 blocks create midscale power-supply biasing points used internally to the AFE031. Each reference divides its respective power-supply voltage in half with a precision resistive voltage divider. REF1 provides a PA_VS/2 voltage used for the PA, while REF2 provides an AVDD/2 voltage used for the Tx PGA, Tx Filter, Rx PGA1, Rx Filter, and Rx PGA2.
PAGE 31
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 Zero Crossing Detector Block The AFE031 includes two zero crossing detectors. Zero crossing detectors can be used to synchronize communications signals to the ac line or sources of noise. Typically, in single-phase applications, only a single zero crossing detector is used. In three-phase applications, both zero crossing detectors can be used; one component detects phase A, and one detects phase B.
PAGE 32
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com For maximum protection of the AFE031 against line transients, it is recommended to use Schottky diodes as indicated in Figure 38. These diodes should limit the ZC_IN pins (pins 38 and 39) to within the maximum rating of (AVDD + 0.4 V) and (AGND – 0.4 V). Some applications may require an isolated zero crossing detection circuit.
PAGE 33
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 ETx and ERx Blocks The AFE031 contains a two-wire transmitter block, ETx, and a two-wire receiver block, ERx. These blocks support communications that use amplitude shift keying (ASK) with on-off keying (OOK) modulation. The ETx block is a gated driver that allows for transmission of a carrier input signal and modulating input signal.
PAGE 34
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com The E_Rx_Out pin can be directly connected to either an available analog-to-digital converter (ADC) input or GPIO on the host microcontroller. Figure 44 illustrates a typical two-wire application for ETx and ERx. AFE031 Internal Configuration E_Tx_In TMS320F28x E_Tx_Out GPIO Flexible PLC Software Engine CEXT E_Rx_In E_Tx_CLK GPIO + N1 + N2 Two-Wire Bus E_Rx_Out GND GPIO Figure 44.
PAGE 35
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 SERIAL INTERFACE The AFE031 is controlled through a serial interface that allows read/write access to the control and data registers. A host SPI frame consists of a R/W bit, a 6-bit register address, and eight data bits. Data are shifted out on the falling edge of SCLK and latched on the rising edge of SCLK. Refer to the Timing Diagrams for a valid host SPI communications protocol. Table 7 through Table 16 show the complete register information.
PAGE 36
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com Table 10. Gain Select Register: Address 0x02 Default: 0x32 Gain Select Register <7:0> BIT NAME RX1G-0, RX1G-1 RX2G-0, RX2G-1 TXG-0, TXG-1 LOCATION (0 = LSB) 0, 1 2, 3 DEFAULT 0, 1 0, 0 R/W FUNCTION R/W This bit is used to set the gain of the Rx PGA1. 00 = 0.25 V/V 01 = 0.5 V/V 10 = 1 V/V 11 = 2 V/V R/W This bit is used to set the gain of the Rx PGA2.
PAGE 37
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 Table 12. Control1 Register: Address 0x04 Default: 0x00 Control1 Register <7:0> BIT NAME LOCATION (0 = LSB) DEFAULT R/W FUNCTION TX_CAL 0 0 R/W This bit is used to enable/disable the TX calibration mode. 0 = disabled, 1 = enabled. RX_CAL 1 0 R/W This bit is used to enable/disable the RX calibration mode. 0 = disabled, 1 = enabled. TX_PGA_CAL 2 0 R/W This bit is used to enable/disable the TX PGA calibration mode.
PAGE 38
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com Table 14. RESET Register: Address 0x09 Default: 0x00 Reset Register <7:0> BIT NAME LOCATION (0 = LSB) DEFAULT R/W -- 0 0 -- Reserved -- 1 0 -- Reserved 2, 3, 4 0, 0, 0 W These bits are used to perform a software reset of the ENABLE1, ENABLE2, CONTROL2, CONTROL3, and GAIN SELECT registers. Writing '101' to these registers performs a software reset. R/W This bit is used to indicate the status of a PA thermal overload.
PAGE 39
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 POWER SUPPLIES The AFE031 has two low-voltage analog power-supply pins and one low-voltage digital supply pin. Internally, the two analog supply pins are connected to each other through back-to-back electrostatic discharge (ESD) protection diodes. These pins must be connected to each other on the application printed circuit board (PCB). It is also recommended to connect the digital supply pin and the two analog supply pins together on the PCB.
PAGE 40
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com PIN DESCRIPTIONS DAC (Pin 7) The DAC pin is used to configure the SPI to either read or write data to the Command and Data Registers, or to write data to the DAC register. Setting the DAC pin high allows access to the DAC register. Setting the DAC pin low allows access to the Command and Data Registers. SD (Pin 8) The Shutdown pin (SD) can be used to shut down the entire AFE031 for maximum power savings.
PAGE 41
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 Table 18 lists the register contents associated with each interrupt condition. Table 18.
PAGE 42
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com CALIBRATION MODES The AFE031 can be configured for three different calibration modes: Tx Calibration, Rx Calibration, and Tx PGA Calibration. Calibration values can be determined during the calibration process and stored in system memory.
PAGE 43
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 Tx PGA Calibration Mode The Tx PGA ac gain can be calibrated in Tx PGA Calibration mode. Figure 48 shows the signal path during Tx PGA Calibration mode. C2000 MCU AFE031 Line Coupling Interface DAC PGA PA LPF SPI SPI PGA PGA LPF Figure 48. Tx PGA Calibration Mode Configuration BASIC CONFIGURATION Figure 49 shows the AFE031 configured in a typical PLC analog front-end application.
PAGE 44
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com +15 V C5 10 mF C13 10 mF 3.3 V R10 7.5 kW R1 33 kW C15 10 mF C14 10 mF C16 100 nF L1 1 mH R2 33 kW D1 C6 10 mF D2 + N1 D3 GPIO R12 4.
PAGE 45
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 LINE-COUPLING CIRCUIT The line-coupling circuit is one of the most critical circuits in a powerline modem. The line-coupling circuit has two primary functions: first, to block the low-frequency signal of the mains (commonly 50 Hz or 60 Hz) from damaging the low-voltage modem circuitry; second, to couple the modem signal to and from the ac mains. A typical line-coupling circuit is shown in Figure 50.
PAGE 46
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com Table 19 lists several recommended transient protection components. Table 19. Recommended Transient Protection Devices 120 VAC, 60 Hz COMPONENT DESCRIPTION MANUFACTURER MFR PART NO (OR EQUIVALENT) D1 Zener diode Diodes, Inc. 1SMB59xxB (1) D2, D3 Schottky diode Diodes, Inc.
PAGE 47
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 Less than 1% ~20% ~20% ~80% Figure 53. Heat Flow in the QFN Package The exposed thermal pad must be soldered to the PCB thermal pad. The thermal pad on the PCB should be the same size as the exposed thermal pad on the underside of the QFN package. Refer to Application Report, QFN/SON PCB Attachment, literature number SLUA271A, for recommendations on attaching the thermal pad to the PCB.
PAGE 48
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com Increasing the number of layers in the PCB, using thicker copper, and increasing the PCB area are all factors that improve the spread of heat. Figure 55 through Figure 57, respectively, show thermal resistance performance as a function of each of these factors.
PAGE 49
AFE031 www.ti.com SBOS531D – AUGUST 2010 – REVISED MAY 2012 For additional information on thermal PCB design using exposed thermal pad packages, refer to Application Report SBOA130, Analog Front-End Design for a Narrowband Power-Line Communications Modem Using the AFE031 and Application Report SLMA002E, PowerPAD™ Thermally-Enhanced Package (both available for download at www.ti.com). Powerline Communications Developer’s Kit A PLC developer’s kit (TMDSPLCKIT-V3) is available to order at www.ti.com/plc.
PAGE 50
AFE031 SBOS531D – AUGUST 2010 – REVISED MAY 2012 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2012) to Revision D Page • Updated Figure 32 .............................................................................................................................................................. 26 • Updated Figure 34 ...........................................................................
PAGE 51
PACKAGE OPTION ADDENDUM www.ti.
PAGE 52
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant AFE031AIRGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 AFE031AIRGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.
PAGE 53
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AFE031AIRGZR VQFN RGZ 48 2500 367.0 367.0 38.0 AFE031AIRGZT VQFN RGZ 48 250 210.0 185.0 35.
PAGE 54
PAGE 55
PAGE 56
PAGE 57
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.