Datasheet

1
100kHz
1MHz
10
PSRR(%FSR/V)
f
Firstpoleof
DACoutputload
030-019
AC
OUTFS
OUT
DAC
V
I
I
PSRR
D
×
=
100
%FSR
V
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
5.3 Analog Supply (vdda_dac) Noise Requirements
In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the
noise requirements stated in this section.
The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current
divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of
supply variation as shown in the following equation:
Depending on frequency, the PSRR is defined in Table 5-4.
Table 5-4. Video DAC Power Supply Rejection Ratio
Supply Noise Frequency PSRR % FSR/V
0 to 100 kHz 1
> 100 kHz The rejection decreases 20 dB/dec.
Example: at 1 MHz the PSRR is 10% of FSR/V
A graphic representation is shown in Figure 5-2.
Figure 5-2. Video DAC Power Supply Rejection Ratio
To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements
translate to the following limits on vdda_dac (for the Video DAC).
The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5:
Table 5-5. Video DAC Maximum Peak-to-Peak Noise on vdda_dac
Tone Frequency Maximum Peak-to-Peak Noise on vdda_dac
0 to 100 kHz < 30 mVpp
> 100 kHz Decreases 20 dB/dec.
Example: at 1 MHz the maximum is 3 mVpp
The maximum noise spectral density (white noise) is defined in Table 5-6:
Table 5-6. Video DAC Maximum Noise Spectral Density
Supply Noise Bandwidth Maximum Supply Noise Density
0 to 100 kHz < 20 V / Hz
> 100 kHz Decreases 20 dB/dec.
Example: at 1 MHz the maximum noise density is 2 / Hz
104 Video DAC Specifications Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM3517 AM3505