Datasheet

Cycle(orPeriod)Jitter

n-1

n+1

Max.CycleJitter=Max(T )

Min.CycleJitter=Min(T )

JitterStandardDeviation(orrmsJitter)=StandardDeviation(T )

030-020

AM3517, AM3505

SPRS550E –OCTOBER 2009–REVISED MARCH 2013

www.ti.com

6 Timing Requirements and Switching Characteristics

Note: The timing data shown is preliminary data and is subject to change in future revisions.

6.1 Timing Test Conditions

All timing requirements and switching characteristics are valid over the recommended operating conditions

of Table 3-3, unless otherwise specified.

6.2 Interface Clock Specifications

6.2.1 Interface Clock Terminology

The Interface clock is used at the system level to sequence the data and/or control transfers accordingly

with the interface protocol.

6.2.2 Interface Clock Frequency

The two interface clock characteristics are:

• The maximum clock frequency

• The maximum operating frequency

The interface clock frequency documented in this document is the maximum clock frequency, which

corresponds to the maximum frequency programmable on this output clock. This frequency defines the

maximum limit supported by the AM3517/05 IC and doesn't take into account any system consideration

(PCB, peripherals).

The system designer will have to consider these system considerations and AM3517/05 IC timings

characteristics as well, to define properly the maximum operating frequency, which corresponds to the

maximum frequency supported to transfer the data on this interface.

6.2.3 Clock Jitter Specifications

Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this

document is the time difference between the typical cycle period and the actual cycle period affected by

noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter.

Figure 6-1. Cycle (or Period) Jitter

Submit Documentation Feedback

Product Folder Links: AM3517 AM3505