Datasheet

AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
6.4 External Memory Interfaces
The AM3517/05 processor includes the following external memory interfaces:
• General-purpose memory controller (GPMC)
• SDRAM controller (SDRC)
6.4.1 General-Purpose Memory Controller (GPMC)
The GPMC is the AM3517/05 unified memory controller used to interface external memory devices such
as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions
TIMING CONDITION PARAMETER 1.8V, 3.3V UNIT
MIN MAX
Input Conditions
t
R
Input signal rise time 0.3 1.8 ns
t
F
Input signal fall time 0.3 1.8 ns
Output Conditions
C
LOAD
Output load capacitance 30 pF
Table 6-3. GPMC/NOR Flash Interface Timing Requirements Synchronous Mode
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
F12 t
su(DV-CLKH)
Setup time, read gpmc_d[15:0] valid before 2.021 ns
gpmc_clk high
F13 t
h(CLKH-DV)
Hold time, gpmc_d[15:0] valid after gpmc_clk high 3.403 ns
F21 t
su(WAITV-CLKH)
Setup time, gpmc_waitx
(1)
valid before gpmc_clk 3.782 ns
high
F22 t
h(CLKH-WAITV)
Hold Time, gpmc_waitx
(1)
valid after gpmc_clk 3.343 ns
high
(1) Wait monitoring support is limited to a WaitMonitoringTime value > 0.
108 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM3517 AM3505