Datasheet

gpmc_clk
gpmc_ncsx
gpmc_a[26:17]
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Address(MSB)
Address(LSB)
D0 D1 D2 D3
OUT
F4
F15 F15 F15
F1
F1
F2
F6
F8F8
F0
F3
F17
F17
F17
F9F6
F17
F17
F17
F14F14
030-025
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-6. GPMC/Multiplexed NOR Flash Synchronous Burst Write
6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing
The following tables assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-5. GPMC/NOR Flash Asynchronous Mode Timing Conditions
TIMING CONDITION PARAMETER VALUE UNIT
Input Conditions
t
R
Input signal rise time 1.8 ns
t
F
Input signal fall time 1.8 ns
Output Conditions
C
LOAD
Output load capacitance 30 pF
Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters
(1) (2)
NO. PARAMETER 1.8V,3.3V UNIT
MIN MAX
FI1 Maximum output data generation delay from internal functional clock 6.5 ns
FI2 Maximum input data capture delay by internal functional clock 4 ns
FI3 Maximum device select generation delay from internal functional clock 6.5 ns
FI4 Maximum address generation delay from internal functional clock 6.5 ns
FI5 Maximum address valid generation delay from internal functional clock 6.5 ns
FI6 Maximum byte enable generation delay from internal functional clock 6.5 ns
(1) The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
116 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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