Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing Internal Parameters
(1) (2)
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
GNFI1 Maximum output data generation delay from internal functional clock 6.5 ns
GNFI2 Maximum input data capture delay by internal functional clock 4 ns
GNFI3 Maximum device select generation delay from internal functional clock 6.5 ns
GNFI4 Maximum address latch enable generation delay from internal functional 6.5 ns
clock
GNFI5 Maximum command latch enable generation delay from internal 6.5 ns
functional clock
GNFI6 Maximum output enable generation delay from internal functional clock 6.5 ns
GNFI7 Maximum write enable generation delay from internal functional clock 6.5 ns
GNFI8 Maximum functional clock skew 100 ps
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
Table 6-11. GPMC/NAND Flash Interface Timing Requirements
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
GNF12
(1)
t
acc(DAT)
Data maximum access time J
(2)
GPMC_FCLK cycles
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime * (TimeParaGranularity + 1)
Table 6-12. GPMC/NAND Flash Interface Switching Characteristics
NO. PARAMETER 1.8V, 3.3V UNIT
MIN MAX
t
R(DO)
Rise time, output data 2.0 ns
t
F(DO)
Fall time, output data 2.0 ns
GNF0 t
w(nWEV)
Pulse duration, gpmc_nwe A(1) ns
valid time
GNF1 t
d(nCSV-nWEV)
Delay time, gpmc_ncsx(13) B(2) - 0.2 B(2) + 2.0 ns
valid to gpmc_nwe valid
GNF2 t
w(CLEH-nWEV)
Delay time, gpmc_nbe0_cle C(3) - 0.2 C(3) + 2.0 ns
high to gpmc_nwe valid
GNF3 t
w(nWEV-DV)
Delay time, gpmc_d[15:0] D(4) - 0.2 D(4) + 2.0 ns
valid to gpmc_nwe valid
GNF4 t
w(nWEIV-DIV)
Delay time, gpmc_nwe invalid E(5) - 0.2 E(5) + 2.0 ns
to gpmc_d[15:0] invalid
GNF5 t
w(nWEIV-CLEIV)
Delay time, gpmc_nwe invalid F(6) - 0.2 F(6) + 2.0 ns
to gpmc_nbe0_cle invalid
GNF6 t
w(nWEIV-nCSIV)
Delay time, gpmc_nwe invalid G(7) - 0.2 G(7) + 2.0 ns
to gpmc_ncsx(13) invalid
GNF7 t
w(ALEH-nWEV)
Delay time, gpmc_nadv_ale C(3) - 0.2 C(3) + 2.0 ns
High to gpmc_nwe valid
GNF8 t
w(nWEIV-ALEIV)
Delay time, gpmc_nwe invalid F(6) - 0.2 F(6) + 2.0 ns
to gpmc_nadv_ale invalid
GNF9 t
c(nWE)
Cycle time, Write cycle time H(8) ns
GNF10 t
d(nCSV-nOEV)
Delay time, gpmc_ncsx(13) I(9) - 0.2 I(9) + 2.0 ns
valid to gpmc_noe valid
GNF13 t
w(nOEV)
Pulse duration, gpmc_noe K(10) ns
valid time
GN F14 t
c(nOE)
Cycle time, Read cycle time L(11) ns
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 125
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