Datasheet

GPMC_FCLK
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_a[16:1]_d[15:0]
gpmc_waitx
DATA
GNF10
GNF13
GNF14
GNF15
GNF12
030-034
GPMC_FCLK
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
gpmc_nwe
gpmc_a[16:1]_d[15:0]
Address
GNF0
GNF1
GNF7
GNF3 GNF4
GNF6
GNF8
GNF9
030-033
AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing
Figure 6-15. GPMC/NAND Flash – Data Read Cycle Timing(1) (2) (3)
(1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock
edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 127
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