Datasheet

A1
A1
E0
T
E1
T
E2
Microprocessor
E3
T
LPDDR
Controller
T
AM3517, AM3505
SPRS550E –OCTOBER 2009–REVISED MARCH 2013 www.ti.com
Figure 6-22 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
Figure 6-22. DQS and DQ Routing and Topology
Table 6-21. DQS and DQ Routing Specification
(1)
NO. PARAMETER MIN TYP MAX UNIT NOTES
2 DQS E Skew Length Mismatch 25 Mils
Center to Center DQS to other LPDDR
3 4w See Note
(2)
trace spacing
4 DQS/DQ nominal trace length DQLM - 50 DQLM DQLM + 50 Mils See Note
(3)
5 DQ to DQS Skew Length Mismatch 100 Mils
6 DQ to DQ Skew Length Mismatch 100 Mils
Center to Center DQ to other LPDDR
7 4w See Note
(2)
trace spacing
Center to Center DQ to other DQ trace
8 3w See Note
(2)
,
(4)
spacing
9 DQ E Skew Length Mismatch 100 Mils
(1) Series terminator, if used, should be located closest to LPDDR.
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(4) DQLM is the longest Manhattan distance of the DQS and DQ net classes.
136 Timing Requirements and Switching Characteristics Copyright © 2009–2013, Texas Instruments Incorporated
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