Datasheet

AM3517, AM3505
www.ti.com SPRS550E –OCTOBER 2009–REVISED MARCH 2013
6.4.2.2 DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding guidelines for using this DDR2
specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).
6.4.2.2.1 DDR2 Interface Schematic
Figure 6-23 shows the DDR2 interface schematic for a dual-memory DDR2 system. The single-memory
system is shown in Figure 6-24. Pin numbers for the AM3517/05 can be obtained from the pin description
section.
6.4.2.2.2 Compatible JEDEC DDR2 Devices
Table 6-22 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 or x32 DDR2 speed grade DDR2-333 devices.
Table 6-22. Compatible JEDEC DDR2 Devices
No. Parameter Min Max Unit Notes
1 JEDEC DDR2 Device Speed Grade DDR2-333 MHz See Note
(1)
2 JEDEC DDR2 Device Bit Width x16 x32 Bits
3 JEDEC DDR2 Device Count 1 2 Devices See Note
(2)
4 JEDEC DDR2 Device Ball Count 84 92 Balls See Note
(3)
(1) Higher DDR2 speed grades operating at the specified speeds are supported due to inherent JEDEC DDR2 backwards compatibility.
(2) Device count indicates number of dies. If a package contains 2 dies, that is the maximum number of devices that can be connected.
(3) 92 ball devices retained for legacy support. New designs should use 84 ball DDR2 devices. Electrically, the 92 and 84 ball DDR2
devices are the same.
Copyright © 2009–2013, Texas Instruments Incorporated Timing Requirements and Switching Characteristics 137
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